Abstract: In a node communicably coupled to alternative nodes through a bus, a transmitting unit receives first designation information from an alternative node. When the first designation information designates the node, the transmitting unit successively transmits, on the bus, the first designation information and data. When a request of an active communication occurs in the node, a request unit determines whether to receive a former part of the first identification information indicative of start timing of an active communication mode on the bus. When determining to receive the former part of the first identification information, the request unit transmits, on the bus, collision information at a timing that allows the collision information to collide with a latter part of the first identification information, resulting in rewrite of the first identification information based on bus arbitration, and transmits second designation information meeting the request of the active communication.

Abstract: To aim to provide an interface circuit that supports both a single-ended method and a differential method as a transmission method, and one of pairs of input terminals for a differential signal is shared to input/output a single-ended signal. A differential signal receiving circuit that receives a differential signal input through the pair of shared terminals is activated when a differential signal is input to a pair of dedicated input terminals for a differential signal, which is different from the pair of shared terminals. After the differential signal receiving circuit is activated, the active state is maintained by a built-in controller.

Abstract: A control unit includes at least one computing device and at least one separate peripheral module which is connected to the computing device via a serial multiwire bus, the peripheral module including at least one output stage for transferring serial data to means outside of the control unit. In order to keep the number of pins required on a peripheral module to a minimum, thereby reducing costs for the entire control unit, the peripheral module has an asynchronous single-wire interface between one interface for the serial multiwire bus and the output stage. The asynchronous single-wire interface is preferably a UART (universal asynchronous receiver/transmitter) interface. The serial multiwire bus is preferably a microsecond bus.

Abstract: There is disclosed a system and method executable in a wireless mobile communication device for dynamically configuring processing speed for a main processor in the device during device initialization. In an embodiment, the method comprises: initiating a boot-rom procedure; determining whether a battery is present in the device, and in response to the presence of the battery, determining whether the battery charge level is above a predetermined threshold; determining whether a USB connection to the device is present, and in response to the presence of a USB connection, enumerating the USB connection; and wherein, in response to the presence of the battery and the battery charge level being above a predetermined threshold, or in response to the USB connection being enumerated at a higher current, the processing speed of the main processor is increased.

Abstract: A method for sharing data contained on a peripheral device amongst a plurality of blade servers is disclosed. The method includes storing a copy of data from a peripheral device to a memory device. The memory device is partitioned into at least ‘n’ memory areas, each memory area storing one copy of the data. The method also includes assigning one of the at least ‘n’ memory areas to each of a plurality ‘n’ of servers. The method also includes establishing communication between the plurality of servers and the plurality of assigned memory areas via a switch controller. The switch controller is configured to access the plurality of assigned memory areas via a processor.

Abstract: A vehicle equipped with a power source system including a master power source and a slave power source connected in parallel to a motor for running is provided. In a case where distribution of discharge power of the master power source and discharge power of the slave power source cannot be controlled, when a voltage difference between the respective power sources is greater than or equal to a certain value, an ECU sets a limit value on electric power supplied from the power source system to the motor at allowable discharge power of one of the power sources having a higher voltage, and limits a motor torque such that electric power discharged from the power source system to the motor does not exceed the set limit value.

Abstract: A system for delivering power over a network of devices connected through a serial link includes a first and second differential pairs of wires. Each differential pair of wires is double AC coupled by a HPF on one side and by another HPF on an opposite side. An LPF connects a portion of each differential pair of wires between the HPFs to a voltage source, and another LPF connects that portion of each differential pair to a load. The system further includes a third and fourth differential pairs of wires. All four differential pairs of wires are located within a single cable, such as a CAT6 cable. The first, second and third differential pair of wires are used for video links, and the fourth differential pair of wires are used for the bi-directional hybrid link. A power delivery circuit in each device includes a voltage source, a power relay switch, a signature resistor for detection, and a load detector.

Abstract: An interface comprises a storage device controller that controls data flow from a Serial ATA bus to a storage device. A configurable bridge circuit is configured in one of a plurality of operating modes including a device bridge mode, and converts Parallel ATA information received on a Parallel ATA bus to Serial ATA information output to the Serial ATA bus when in the device bridge mode.

Abstract: A method for environmentally cognizant power management that gathers server, application and environmental information from different devices to compute an aggregate behavior model.

Abstract: A data processing apparatus and method are provided for arbitrating between multiple access requests seeking to access a plurality of resources sharing a common access path. At least one logic element issues access requests requesting access to the resources, and each access request identifies which of the resources is to be accessed. Arbitration circuitry performs a multi-cycle arbitration operation to arbitrate between multiple access requests to be passed over the common access path, the arbitration circuitry having a plurality of pipeline stages to allow a corresponding plurality of multi-cycle arbitration operations to be in progress at any one time. Filter circuitry is provided which has a plurality of filter states, the number of filter states being dependent on the number of pipeline stages of the arbitration circuitry, and each resource being associated with one of the filter states.

Abstract: Data processing systems with interrupts and methods for operating such data processing systems and machine readable media for causing such methods and containing executable program instructions. In one embodiment, an exemplary data processing system includes a processing system, an interrupt controller coupled to the processing system and a timer circuit which is coupled to the interrupt controller. The interrupt controller is configured to provide a first interrupt signal and a second interrupt signal to the processing system. The processing system is configured to maintain a data structure (such as, e.g., a list) of time-related events for a plurality of processes, and the processing system is configured to cause the entry of a value, representing a period of time, into the timer circuit. The timer circuit is configured to cause an assertion of the first interrupt signal in response to an expiration of the time period.

Abstract: A system and method for interfacing multiple inputs and outputs in a control system is provided. A digital input/output system provides a localized interface between multiple operator consoles and at least one output device to coordinate and monitor the operation of the at least one output device. The digital input/output system includes an interface device which re-routes discrete lines to and from the operator consoles and output devices and eliminates conflicting signals sent from the operator consoles to the output devices.

Abstract: Methods and apparatus for intelligently powering an electronic device are provided. In one embodiment of the invention, a systems management controller controls a power interface to intelligently negotiate power distribution with a peer, client, or a host device. The primary data path is unaffected by the system management controller communications. Various aspects of the present invention are demonstrated with respect to an exemplary implementation of a unified interface, consisting of an optical link (data path) and a USB link (power). As described, one exemplary embodiment of the invention provides a device with power at levels which are much increased over prior art USB solutions.

Abstract: A system for executing applications designed to run on a single SMP computer on an easily scalable network of computers, while providing each application with computing resources, including processing power, memory and others that exceed the resources available on any single computer. A server agent program, a grid switch apparatus and a grid controller apparatus are included. Methods for creating processes and resources, and for accessing resources transparently across multiple servers are also provided.

Abstract: A system and method for interfacing multiple inputs and outputs in a control system is provided. A digital input/output system provides a localized interface between multiple operator consoles and at least one output device to coordinate and monitor the operation of the at least one output device. The digital input/output system includes an interface device which re-routes discrete lines to and from the operator consoles and output devices and eliminates conflicting signals sent from the operator consoles to the output devices.

Abstract: In an embodiment, a south chip comprises a first virtual bridge connected to a shared egress port and a second virtual bridge also connected to the shared egress port. The first virtual bridge receives a first secondary bus identifier, a first subordinate bus identifier, and a first MMIO bus address range from a first north chip. The second virtual bridge receives a second secondary bus identifier, a second subordinate bus identifier, and a second MMIO bus address range from a second north chip. The first virtual bridge stores the first secondary bus identifier, the first subordinate bus identifier, and the first MMIO bus address range. The second virtual bridge stores the second secondary bus identifier, the second subordinate bus identifier, and the second MMIO bus address range. The first north chip and the second north chip are connected to the south chip via respective first and second point-to-point connections.

Abstract: Detecting localizable native methods may include statically analyzing a native binary file of a native method. For each function call invoked in the native binary, it is checked whether resources accessed through the function call is locally available or not. If all resources accessed though the native method is locally available, the method is annotated as localizable.

Abstract: In a rule-based system for monitoring process adherence, first and second processing patterns are received and merged to provide a merged processing pattern. Each processing pattern, which may be expressed in a state graph representation, embodies at least a portion of a desired software code development process. Optionally, the merged processing pattern may be presented to a subject-matter expert to obtain feedback thereon. The merged processing pattern may then be converted into an executable process verification rule for use in monitoring process adherence. In an embodiment, development process event data is compared to the executable process verification rules. Violations of the rules result in the generation of failure indications that may be stored and subsequently reported as needed. In this manner, efficiency of automated process adherence monitoring systems may be improved when determining the level of compliance by developers with one or more software code development processes.

Abstract: A switch (304) includes a plurality of bridges (3041, 3042, 3043, 3044, 3045) and a switch forwarding mechanism (20). Each of the bridges transmits and receives a TLP frame complying with PCI express to and from a device connected to each of the bridges. The switch forwarding mechanism includes a plurality of ports (1, 2, 3, 4, 5) to which the bridges are connected, respectively, selects an output port in dependence on a combination of destination information on the TLP frame input from one of the plurality of ports and the port which input the TLP frame, and outputs the TLP frame from the selected output port.

Abstract: A method, apparatus, and computer instructions for qualifying events by types of interrupt when interrupt occurs in the processor of a data processing system. A programmable performance monitoring unit (PMU) is used to program hardware counters that collect events associated with a type of interrupt, including nested interrupts. The performance monitoring unit may also count events that occur while servicing interrupt requests based upon the state of interrupt processing. Events that are known to the performance monitoring unit such as instruction retired, TLB misses, may be counted at the same time using a number of performance monitoring counters in the performance monitoring unit.