Abstract: A method for transmitting data frames between a master device and one or more slave devices via a bus system having at least one request line for transmitting request data frames from the master device to the slave devices, a response line for transmitting response data frames from the slave devices to the master device and at least one selection line for activating the slave devices, the request data frames and the response data frames being transmitted together with at least one address bit for addressing one of the slave devices, the useful data bits and at least one length-indicating bit for indicating the data frame length.

Abstract: A memory system and method includes a unidirectional downstream bus coupling write data from a memory controller to several memory devices, and a unidirectional upstream bus coupling read data from the memory devices to the memory controller. The memory devices each include a write buffer for storing the write data until the respective memory device is no longer busy processing read memory requests. The downstream bus may also be used for coupling memory commands and/or row and column addresses from the memory controller to the memory devices.

Abstract: Power management of a system. A request may be received to enter a first sleep state for a system. One or more processes may be performed to enter the first sleep state in response to the request to enter the first sleep state. A system memory of the system may be stored in a nonvolatile memory (NVM) in response to the request to enter the first sleep state in order to enter a second sleep state. Power may be removed from the system memory after storing the system memory in the NVM in response to the request to enter the first sleep state. After removing power to the system memory, the system may be in the second sleep state.

Abstract: Resuming from a sleep state. A request may received to resume operation of a computer system from a sleep state to an executing state. A restoring process may be initiated to restore the computer system to an executing state. The restoring process may include loading information from a nonvolatile memory medium to a computer system memory medium. A request may be received from a processor of the computer system to access the computer system memory medium. The request may require access to a portion of the computer system memory medium in the executing state, and may be received prior to completion of the restoring process. It may be determined if the portion of the computer system memory medium has been restored. If the portion of the computer system memory medium has not been restored, the portion of the computer system memory medium may be restored from the nonvolatile memory medium ahead of other portions in the restoring process.

Abstract: User-specific software debugging with user-specific step commands that includes: receiving a command to step execution to a source code module associated with a user; identifying routines in a call stack associated with the user; inserting, for each identified routine, a breakpoint at each source code line of the routine; inserting, for each source code module associated with the user and not in the call stack, a breakpoint at an entry point of the source code module; and executing the debuggee until the debuggee encounters one of the inserted breakpoints thereby halting execution of the debuggee. User-specific debugging with user-specific Dynamically Linked Library (DLL) load processing modes including: receiving a selection of a user-specific DLL processing mode; upon loading a DLL, retrieving a user identification; determining whether the DLL is associated with the user; and processing the DLL in accordance with user specific DLL processing mode only if the DLL is associated with the user.

Abstract: A method for controlling access to data of a message memory, and a message handler of a communications module having a message memory, in which data are input or output in response to an access; the message memory being connected to a first buffer configuration and a second buffer configuration, and the data being accessed via the first or the second buffer configuration; in the message handler, at least one first finite state machine being provided which controls the access to the message memory via the first buffer configuration, and at least one second finite state machine being provided which controls the access via the second buffer configuration, the at least one first finite state machine and the second finite state machine making access requests; and a third finite state machine being provided which assigns access to the message memory to the at least one first and the second finite state machine as a function of their access requests.

Abstract: According to one embodiment, an interface comprises establishing a connection to a communicatee device, transmitting a connection maintenance signal to the communicatee device, and decreasing a maximum amplitude of the connection maintenance signal from a first amplitude, establishing a connection to the communicatee device again when communication is disabled, and transmitting the connection maintenance signal to the communicatee device, and setting the maximum amplitude of the connection maintenance signal to a second amplitude which is larger than the maximum value of the connection maintenance signal obtained when the communication is disabled by a predetermined value.

Abstract: A method for arbitration including selecting, for an arbitration interval corresponding to a timeslot, a sending node from a plurality of sending nodes in an arbitration domain, where the plurality of sending nodes include a plurality of source counters; broadcasting, by the sending node and in response to selecting the sending node, a transmitter arbitration request for the timeslot during the arbitration interval; receiving, by the plurality of sending nodes, the transmitter arbitration request; incrementing the plurality of source counters in response to receiving the transmitter arbitration request; and sending, during the timeslot, a data item from the sending node to a receiving node via an optical data channel.

Abstract: An information processor includes: a plurality of master cores, a plurality of slave cores, a plurality of slave adapters each connected to a respective slave core of the plurality of slave cores, and an interconnected network for connecting the master cores and slave adapters by way of a plurality of router nodes. The slave adapters compare a first access request transmitted by a first master core among the plurality of master cores and a second access request transmitted by a second master core other than the first master core among the plurality of master cores based on a request from the first master core and a request from the second master core, and transmit the first access request or the second access request to the slave core that is connected to the slave adapter when the first access request and the second access request match.

Abstract: The present invention extends to methods, systems, and computer program products for binding executable code at runtime. Embodiments of the invention include late binding of specified aspects of code to improve execution performance. A runtime dynamically binds lower level code based on runtime information to optimize execution of a higher level algorithm. Aspects of a higher level algorithm having a requisite (e.g., higher) impact on execution performance can be targeted for late binding. Improved performance can be achieved with minimal runtime costs using late binding for aspects having the requisite execution performance impact.

Abstract: Memory management for object oriented applications during run time includes loading an object oriented application into a computer memory. The object oriented application includes a plurality of nodes in a classification tree, the nodes including key value pairs. The nodes are aggregated in the classification tree by a computer. The aggregating includes eliminating redundant keys and creating a composite node. The composite node is loaded into the computer memory. The plurality of nodes in the classification tree are removed from the computer memory in response to loading the composite node into the computer memory.

Abstract: A system includes a master device and a number of slave devices connected to the master device via a bus. Each slave device includes a control unit, a switch unit, and a lock unit. When a new slave device is connected to the system, the control unit of the new slave device transmits a request signal to the master device. The master device detects whether the master device is communicating with the already connected slave devices after receiving the request signal, and outputs an enable signal to the new slave device according to the detected result. The control unit of the new slave device controls the lock unit of the new slave device to turn on and turn off the switch unit of the new slave device according to the enable signal.

Abstract: According to an aspect of the embodiment, a system control apparatus includes a control signal transmitting unit which transmits a control signal to control circuits via first signal line. The control signal includes a command for performing a control setting on other control circuits other than own control circuit or to all control circuits. Each control circuit includes a signal receiving unit which receives the control signal transmitted from the control signal transmitting unit via the first signal line, a signal transfer unit which transfers the command included in the received control signal via second signal lines to the control circuit, and a control setting unit which performs the control setting on the own control circuit according to the command included in the received control signal or a command transferred from the other control circuits other than the own control circuit.

Abstract: Mechanisms for providing an interconnect layer of a three-dimensional integrated circuit device having multiple independent and cooperative on-chip networks are provided. With regard to an apparatus implementing the interconnect layer, such an apparatus comprises a first integrated circuit layer comprising one or more first functional units and an interconnect layer coupled to the first integrated circuit layer. The first integrated circuit layer and interconnect layer are integrated with one another into a single three-dimensional integrated circuit. The interconnect layer comprises a plurality of independent on-chip communication networks that are independently operable and independently able to be powered on and off, each on-chip communication network comprising a plurality of point-to-point communication links coupled together by a plurality of connection points. The one or more first functional units are coupled to a first independent on-chip communication network of the interconnect layer.

Abstract: According to an aspect of the embodiment, an input/output device transmits a message to a first node controller of a parent node which is set in advance via a cross bar. At this point, the cross bar generates information based on node information of the input/output device, and adds the generated information to the message. The first node controller transmits, via the cross bar, the message to a second node controller of a parent node corresponding to an input/output device that is to receive the message. The second node controller transmits, via the cross bar, the message to an input/output device that is to receive the message. At this point, the cross bar transmits the message restored by deleting the generated information from the message to the input/output device which is set as a destination.

Abstract: A device having power management capabilities and a method for power management, the method includes: providing a clock signal and a supply voltage to at least one component of a device; detecting a timing error; delaying by a fraction of a clock cycle and in response to the detected timing error, a clock signal provided to at least one of the components; and determining a clock signal frequency and a level of the supply voltage in response to at least one detected timing error.

Abstract: According to certain embodiments, an apparatus comprises port interfaces, charge storage devices, and a charge combiner coupled to a circuit board. Each charge storage device is associated with a port interface. Each port interface receives a current of charge from a device under test and pumps the charge to an associated charge storage device at a predetermined rate. Each charge storage device stores the charge from an associated port interface. The charge combiner combines the charge from the charge storage devices to yield a combined charge and feeds the combined charge to an output regulator.

Abstract: There is provided a request arbitration apparatus for arbitrating a plurality of request holding sections which hold requests having priorities when the requests are output from the plurality of request holding sections to the output device. The request arbitration apparatus includes: a setting section that sets the request holding section, which holds the highest priority request among all the requests held by the plurality of request holding sections, as a highest priority request holding section; and a control section that controls the highest priority request holding section so that the request held first among all the requests held by the highest priority request holding section is output to the output device.

Abstract: A USB printer sharing switch device with automatic switching capabilities is provided for multiple computers to share a USB printer. The sharing switch device transfers USB data between the computers and the printer without changing the data format. The automatic switching function is performed by hardware and firmware of the sharing switch device in cooperation with driver software on the computers. In one implementation, the sharing switch device includes multiple USB device controllers corresponding to the multiple computers, and employs multiple switches and a USB hub so that each computer is connected to its corresponding controller and the computer that is currently connected to the printer can communicate with its controller while printing. The current computer transmits a spooling finished command to its controller when spooling is finished. After receiving the spooling finished command, the sharing switch device automatically switches the printer to another computer.

Abstract: Described embodiments provide for transfer of data between data modules. At least two crossbar switches are employed, where input nodes and output nodes of each crossbar switch are coupled to corresponding data modules. The ith crossbar switch has an Ni-input by Mi-output switch fabric, wherein Ni and Mi are positive integers greater than one. Each crossbar switch includes an input buffer at each input node, a crosspoint buffer at each crosspoint of the switch fabric, and an output buffer at each output node. The input buffer has an arbiter that reads data packets from the input buffer according to a first scheduling algorithm. An arbiter reads data packets from a crosspoint buffer queue according to a second scheduling algorithm. The output node receives segments of data packets provided from one or more corresponding crosspoint buffers.