Abstract: An image processing apparatus includes: a main controller which controls a processing of an image; a power supply which supplies power to the main controller; a switching unit which selectively allows the power to be supplied from the power supply to the main controller; and a sub controller which determines whether a first power-off event occurs, and controls the switching unit to cut off the power supplied to the main controller if the sub controller determines that the first power-off event occurs, wherein the main controller determines whether a second power-off event different from the first power-off event occurs, and the switching unit cuts off the power supplied to the main controller if the second power-off event occurs.

Abstract: A device for manipulating communication messages in a communication system is provided, which communication system includes a data bus, and a plurality of nodes connected thereto, and an arrangement for transmitting messages in message frames at fixedly predefined communication cycles. The device is connected in the data bus between at least one node for which the messages to be manipulated are intended and the other nodes of the communication system. The device has an arrangement for intercepting the messages before they reach the at least one node, an arrangement for manipulating the intercepted messages, and an arrangement for transmitting the manipulated messages to the at least one node.

Abstract: In an embodiment, a translation of a hierarchical bus number to a physical bus number and a bridge identifier of a bridge are written to a north chip. A request is received that comprises an identifier of a destination. A determination is made that the identifier comprises the hierarchical bus number. In response to the determination, the identifier of the destination is replaced in the request with the physical bus number and the bridge identifier. The request is sent to the bridge identified by the bridge identifier. A south chip comprises the bridge, and the south chip is connected to the north chip via a point-to-point serial link. The physical bus number identifies a bus that connects the bridge to a device. The request comprises a configuration write request that requests a write of data to the device.

Abstract: According to one embodiment, a recording/reproduction apparatus includes a power source controller. The power source controller includes a determination unit, a stand-by mode execution unit, and a pause mode execution unit. The determination unit determines whether or not an event associated with at least one of recording and reproduction of the information signal occurs at start-up time. The stand-by mode execution unit executes a stand-by mode in which the power level of each of the encoder, the decoder, the recording medium, and the plurality of signal processors is controlled to be lower than a predetermined level. The pause mode execution unit executes a pause mode in which the power to each of the encoder, the decoder, the recording medium, and the plurality of signal processors is turned off, and the power level of the process controller is controlled to be lower than the predetermined level.

Abstract: A method of generating a dynamic port enable signal for gating memory array data to an output node includes generating a programmable leading edge clock signal derivation of an input dynamic clock signal; generating a programmable trailing edge clock signal derivation of the input dynamic clock signal, wherein the leading edge clock signal derivation and the trailing edge clock signal derivation are independently programmable with respect to one another; and gating the generated programmable leading and trailing edge clock signal derivations with a static input enable signal so as to generate the port enable signal such that, when inactive, the port enable signal prevents early memory array data from being coupled to the output node.

Abstract: In case that a main component and an auxiliary component to be presented in synchronization with the main one have to be presented through data transmission between both devices, the present invention issues an action for setting access location information (e.g., URL) of at least one auxiliary component to a media renderer, wherein the action is different from an action for setting access location information of a main component. As a different way, the present invention sets access location information of at least one auxiliary component to a media renderer through an action including access location information of an auxiliary component as well as access location information of a main component.

Abstract: Provided are a method of managing power of a multi-core processor, a recording medium storing a program for performing the method, and a multi-core processor system. The method of managing power of a multi-core processor having at least one core includes determining a parallel-processing section on the basis of information included in a parallel-processing program, collecting information for determining a clock frequency of the core in the determined parallel-processing section according to each core, and then determining the clock frequency of the core on the basis of the collected information. Accordingly, it is possible to minimize power consumption while ensuring quality of service (QoS).

Abstract: Systems and methods are disclosed to manage power in a custom integrated circuit (IC) design by receiving a specification of the custom integrated circuit including computer readable code and generating a profile of the computer readable code to determine instruction usage; automatically generating a processor architecture uniquely customized to the computer readable code, the processor architecture having one or more processing blocks and one or more power domains; determining when each processing block is needed based on the code profile and assigning each block to one of the power domains; and gating the power domains with power based on the code profile; and synthesizing the generated architecture into a computer readable description of the custom integrated circuit for semiconductor fabrication.

Abstract: The rate at which data is provided by one device and the rate at which that data is processed by another device may differ. For example, a transmitting device may transmit data according to a transmit clock while a receiving device that receives the transmitted data may process the data according to a receive clock. If there is a timing mismatch between the transmit and receive clocks, the receiving device may receive data faster or slower than it processes the data. In such a case, there may be errors relating to the processing of the received data. To address timing mismatches such as this, the receiving device may delete data from or insert data into the received data. In conjunction with these operations, the receiving device may modify the received data at or near the insertion point or the deletion point in a manner that mitigates any adverse effect the insertion or deletion may have on a resulting output signal.

Abstract: System and method for synchronizing devices. A device reads a first counter coupled to and associated with a master clock and a second counter coupled to and associated with the device, where the device is one of one or more devices coupled to the master clock and each other via a switched fabric, where each device includes a respective clock, and is coupled to and associated with a respective second counter. Each of the first counter and the second counters is accessible by each of the one or more devices. The device determines a difference between the device's associated second counter and the first counter, and determines and stores a time reference for the device relative to the master clock based on the determined difference, where the time reference is useable to timestamp events or synchronize future events.

Abstract: The present invention extends to methods, systems, and computer program products for representing various programming elements with compiler-generated tasks. Embodiments of the invention enable access to the future state of a method through a handle to a single and composable task object. For example, an asynchronous method is rewritten to generate and return a handle to an instance of a builder object, which represents one or more future states of the asynchronous method. Information about operation of the asynchronous method is then passed through the handle. Accordingly, state of the asynchronous method is trackable prior to and after completing.

Abstract: Methods and systems for analyzing bus traffic in a target device, such as a system on-a-chip (SOC) comprises capturing a processor event and generating an interrupt based on a threshold associated with the processor event. Based on at least the interrupt, a instruction pointer associated with the processor event that generated the interrupt is identified. An instruction analyzer identifies a memory address of the instruction associated with the processor event that generated the interrupt. At least the processor event and a associated instruction information are collected by a sample collector and transferred to a host for performance profiling.

Abstract: An integrated system may provide seamless project management for developing for an Enterprise Management Application (EMA) using a Program Development Application (PDA). The integrated system may align the EMA development experience with the development experience of using the PDA's toolset, and may deliver the capability of developing Enterprise Management projects working off of the PDA's infrastructure through proxy items. Proxy items may be generated to represent programmable objects from the Application Object Server (AOS) in the EMA for use in the PDA toolset and may appear as managed code artifacts for programming in the PDA. Proxy items may include the unique identifier linking the proxy item in the PDA toolset to its specific location in the AOS. As changes are made in PDA, the proxy items and the code behind them may be saved to the EMA in the location specified by the unique identifier.

Abstract: A system includes a hard disk controller configured to, using only a single pin, transfer serial information from the hard disk controller. The serial information includes control data associated with control of both write operations and read operations. The serial information includes a first bit indicating a start of the control data, a predetermined number of bits of the control data following the first bit, and a second bit indicating an end of the predetermined number of bits of the control data. A read/write channel is configured to receive the serial information and perform the write operations and the read operations based on the serial information.

Abstract: Processing of out-of-order data transfers is facilitated in computing environments that enable data to be directly transferred between a host bus adapter (or other adapter) and a system without first staging the data in hardware disposed between the host bus adapter and the system. An address to be used in the data transfer is determined, in real-time, by efficiently locating an entry in an address data structure that includes the address to be used in the data transfer.

Abstract: Analyzing dynamic source code. A method includes accessing a specific metadata format data structure. The data structure was created by obtaining one or more first data structures defining constructs in a body of dynamic language source code. From the one or more first data structures, identifier information is extracted for one or more of the defined constructs. Knowledge about the constructs is augmented. The metadata format data structure is parsed to compute metrics about the metadata format data structure. The metrics about the metadata format data structure are provided to a user.

Abstract: The invention relates to a storage device in which MR-IOV is applied to the internal network of a storage controller, whereby the size of the storage device can be easily expanded. The storage device is expanded on the basis of a network having processor-connected RPs, FE I/F, BE I/F, and CM I/F that are connected with a switch. In the switch, a plurality of ports other than those connected to the RPs, FE I/F, BE I/F, and CM I/F are connected with a cross-link. Each processor is allowed to control the FE I/F, BE I/F, or CM I/F either via a path that passes through the cross-link or via a path that does not pass through the cross-link within the unit device. When unit devices are connected to expand the size of a storage device, the cross-link is removed first and then the unit devices are connected with a new cross-link (see FIG. 4).

Abstract: The present invention extends to methods, systems, and computer program products for optimizing execution of kernels. Embodiments of the invention include an optimization framework for optimizing runtime execution of kernels. During compilation, information about the execution properties of a kernel are identified and stored alongside the executable code for the kernel. At runtime, calling contexts access the information. The calling contexts interpret the information and optimize kernel execution based on the interpretation.

Abstract: Cross bar control circuits are connected to each other by two buses, which are a broadcast bus for transmitting a broadcast packet from a system board to all system boards other than the system board and a point-to-point bus for transmitting a unicast packet from a system board to another system board. When unicast packets passing through the point-to-point bus are too many, the unicast packets are output by using the broadcast bus in addition to the point-to-point bus if the broadcast bus is not used. In this way, the unicast packets can be output quickly and efficiently, so that use efficiency of the broadcast bus and the point-to-point bus can be increased as a whole.

Abstract: Updating a plurality of computers is accomplished. A first message is created in an update source, where the first message includes a one or more instructions and an address of a message repository. The first message is transmitted to a first computer using either a Push or a Pull protocol. A second message is transmitted to the first computer using the Push or Pull protocol, the second message comprising data retrieved from the address in the first message. The first computer executes one or more of the instructions in the first message with at least some of the second message. The address in the first message is updated to match the address of the first computer. The updated first message is transmitting to a further one of the computers. Transmission of the second message is repeated to further ones in the plurality of computers until all of the plurality of computers have been updated.