Abstract: The present invention presents a method for detecting an endpoint of an etch process for etching a substrate in plasma processing system (1) comprising: etching the substrate; measuring at least one endpoint signal; generating at least one filtered endpoint signal by filtering the at least one endpoint signal, wherein the filtering comprises applying a Savitsky Golay filter (12) to the at least one endpoint signal; and determining (14) an endpoint of the etch process from the at least one filtered endpoint signal.

Abstract: The invention provides a method of preparing a chemical-mechanical polishing composition for polishing a substrate with at least a first layer and a second layer. The method comprises providing both a first chemical-mechanical polishing composition comprising an abrasive with a selectivity for a first layer as compared to a second layer and a second chemical-mechanical polishing composition comprising an abrasive with different selectivity for the first layer as compared to the second layer, wherein the second chemical-mechanical polishing composition is stable in the presence of the first chemical-mechanical polishing composition, and mixing the first and second chemical-mechanical polishing compositions in a ratio to achieve a final selectivity for the first layer as compared to the second layer. The invention further provides a method of chemically-mechanically polishing a substrate.

Abstract: Methods for eliminating and/or mitigating bridging and/or leakage caused by the contamination of a dielectric layer with fragments and/or residues of a conductive material are disclosed. The methods involve exposing a semiconductor substrate with a dielectric layer contaminated with fragments and/or residues of conductive materials to one or more conductor and/or dielectric etches. The disclosure by eliminating and/or mitigating metal bridging and/or leakage can provide one or more of the following advantages: high device reliability, decreased manufacturing cost, more efficient metallization, and increased performance.

Abstract: A method of manufacturing a nanochannel-array and a method of fabricating a nanodot using the nanochannel-array are provided. The nanochannel-array manufacturing method includes: performing first anodizing to form a first alumina layer having a channel array formed by a plurality of cavities on an aluminum substrate; etching the first alumina layer to a predetermined depth and forming a plurality of concave portions on the aluminum substrate, wherein each concave portion corresponds to the bottom of each channel of the first alumina layer; and performing second anodizing to form a second alumina layer having an array of a plurality of channels corresponding to the plurality of concave portions on the aluminum substrate. The array manufacturing method makes it possible to obtain finely ordered cavities and form nanoscale dots using the cavities.

Abstract: An organic/inorganic hybrid film represented by SiCx?HyOz (x>0, y?0, z>0) is plasma-etched with an etching gas containing fluorine, carbon and nitrogen. During the etching, a carbon component is eliminated from the surface portion of the organic/inorganic hybrid film due to the existence of the nitrogen in the etching gas, to thereby reform the surface portion. The reformed surface portion is nicely plasma-etched with the etching gas containing fluorine and carbon.

Abstract: An etch release for a MEMS device on a substrate includes etching the substrate with an etchant vapor and a wetting vapor. A thermal bake of the MEMS device, after the etch release may be used to volatilize residues. A supercritical fluid may also be used to remove residual contaminants. The combination of the etchant vapor, such as HF, and the wetting vapor, such as an alcohol vapor, improves the uniformity of the etch undercut on the substrate.

Abstract: A process for fabricating a MOSFET device featuring a channel region comprised with a silicon-germanium component is provided. The process features employ an angled ion implantation procedure to place germanium ions in a region of a semiconductor substrate underlying a conductive gate structure. The presence of raised silicon shapes used as a diffusion source for a subsequent heavily doped source/drain region, the presence of a conductive gate structure, and the removal of dummy insulator previously located on the conductive gate structure allow the angled implantation procedure to place germanium ions in a portion of the semiconductor substrate to be used for the MOSFET channel region. An anneal procedure results in the formation of the desired silicon-germanium component in the portion of semiconductor substrate to be used for the MOSFET channel region.

Abstract: A new method is provided for the processing of metals, most notably copper, such that damage to exposed surfaces of these metals is prevented. During a step of semiconductor processing, which results in exposing a metal surface to a wet substance having a pH value, a voltage is applied to the metal that is exposed. The value of the applied voltage can, dependent on the value of the pH constant of the wet substance, be selected such that the exposed metal surface is protected against alkaline effects of the wet substance.

Abstract: The invention provides a method of chemically-mechanically polishing a substrate. A substrate comprising ruthenium and copper is contacted with a chemical-mechanical polishing system comprising a polishing component, hydrogen peroxide, an organic acid, at least one heterocyclic compound comprising at least one nitrogen atom, and water. The polishing component is moved relative to the substrate, and at least a portion of the substrate is abraded to polish the substrate. The pH of the polishing system is about 6 to about 12, the ruthenium and copper are in electrical contact, and the difference between the open circuit potential of copper and the open circuit potential of ruthenium in the polishing system is about 50 mV or less.

Abstract: A method of etching a feature in a surface of a substrate. The substrate is provided. A photoresist layer is formed on the surface of the substrate. A thickness profile of the formed photoresist layer is determined. A grayscale scanning pattern is determined based on the feature and the thickness profile of the photoresist layer. The determined grayscale scanning pattern is laser written on the photoresist layer to expose a portion of the photoresist layer. The exposed portion of the photoresist layer is removed to form a grayscale pattern in the photoresist layer. The photoresist layer and the surface of the substrate are etched to form the feature in the surface of the substrate.

Abstract: Accordingly, this invention relates to an dry etching process for semiconductor wafers. More particularly, the present invention discloses a dry etching process including a halogen etchant (24) and a nitrogen gas (28) that selectively etches a compound semiconductor material (18) faster than the front-side metal layers (16A)(16B). Further, the dry etching process produces a vertical wall profile on compound semiconductor material (18) in both X (38) and Y (40) crystalline directions without undercutting the top of a via-opening.

Abstract: A wafer, having at least a spindle region and at least two through regions alongside the spindle region, is provided. The wafer in the spindle region is partially removed from the bottom surface. Thereafter, the bottom surface is bonded to a carrier with a bonding layer, and the wafer in the through regions is completely removed from the top surface.

Abstract: An etching method of the present invention includes a first and a second process. In the first process, pattern widths of a pre-patterned mask layer are increased by depositing plasma reaction products on sidewalls of the mask layer. In the second process, a layer to be etched is etched by using the mask layer as a mask having increased the pattern widths. Therefore, mask layers having different pattern densities exist in the same wafer and pattern widths of mask layers patterned through a photolithography process are uneven according to pattern densities, each pattern width of the mask layers can be made uniform. Accordingly, the pattern widths of the layer can be made uniform over an entire wafer.

Abstract: A method of forming air gaps within a solid structure is provided. In this method, a sacrificial material is covered by an overlayer. The sacrificial material is then removed through the overlayer to leave an air gap. Such air gaps are particularly useful as insulation between metal lines in an electronic device such as an electrical interconnect structure. Structures containing air gaps are also provided.

Abstract: A dual damascene trench etching process includes a two-step BARC etching process, a first BARC etch step using a fluorocarbon-based plasma, and a second BARC etch step using an O2/N2-based plasma. The first BARC etch step removes a first portion of the BARC covering a dielectric stack using a fluorocarbon-based plasma. The second BARC etch step removes a second portion of the BARC covering the dielectric stack using a O2/N2 based plasma. The dual damascene trench etching process may further include a BARC etch back process to remove a further portion of the BARC not covering the dielectric stack. The dual damascene trench etching process further includes a low-k dielectric etching process that etches trenches in a low-k dielectric layer in the dielectric stack and that avoids the use of argon in order to prevent facet formation.

Abstract: A semiconductor device includes a plurality of pillars formed from a conductive material. The pillars are formed by using a plurality of nanocrystals as a hardmask for patterning the conductive material. A thickness of the conductive material determines the height of the pillars. Likewise, a width of the pillar is determined by the diameter of a nanocrystal. In one embodiment, the pillars are formed from polysilicon and function as the charge storage region of a non-volatile memory cell having good charge retention and low voltage operation. In another embodiment, the pillars are formed from a metal and function as a plate electrode for a metal-insulator-metal (MIM) capacitor having an increased capacitance without increasing the surface area of an integrated circuit.

Abstract: The semiconductor device fabrication method comprises the step of forming a first insulation film 48 on a semiconductor substrate 10 and a ferroelectric capacitor 42; the step of forming first interconnections 56a–56c; the step of forming a second insulation film 60; the step of planarizing the surface of the second insulation film 60; the step of making heat treatment with a heat treatment furnace to remove water from the second insulation film 60; the step of making heat treatment in a plasma atmosphere generated by using N2O gas or N2 gas; the step of removing water from the second insulation film 60 and nitriding the surface of the second insulation film 60; the step of forming a barrier film 62 on the second insulation film 60; the step of forming contact holes 68 in the barrier film 62 and the second insulation film 60; and the step of burying conductor plugs 70 in the contact holes 68.

Abstract: Methods for etching a metal layer and a metallization method of a semiconductor device using an etching gas that includes Cl2 and N2 are provided. A mask layer is formed on the metal layer, the etching gas is supplied to the metal layer, and the metal layer is etched by the etching gas using the mask layer as an etch mask. The metal layer may be formed of aluminum or an aluminum alloy. Cl2 and N2 may be mixed at a ratio of 1:1 to 1:10. The etching gas may also include additional gases such as inactive gases or gases that include the elements H, O, F, He, or C. In addition, N2 may be supplied at a flow rate of from 45–65% of the total flow rate of the etching gas, which results in a reduction in the occurrence of micro-loading and cone-shaped defects in semiconductor devices.

Abstract: A reticle manufacturing method comprises a step of retreating side surfaces of a lift-off pattern to reduce an area of a wide pattern portion, a step of forming a wide convex pattern and a narrow convex pattern by etching a glass substrate (transparent substrate) while using a second mask pattern as a mask, a step of reducing an area of a first wide mask portion, a step of reducing at least an area of a second wide mask portion smaller than an area of the first wide mask portion, and a step of reducing an area of a wide light shielding portion by etching the wide light shielding portion while using the first wide mask portion as a mask.

Abstract: A method and system for masking a surface to be etched is described. The method includes the operation of heating a phase-change masking material and using a droplet source to eject droplets of a masking material for deposit on a thin-film or other substrate surface to be etched. The temperature of the thin-film or substrate surface is controlled such that the droplets rapidly freeze after upon contact with the thin-film or substrate surface. The thin-film or substrate is then treated to alter the surface characteristics, typically by depositing a self assembled monolayer on the surface. After deposition, the masking material is removed. A material of interest is then deposited over the substrate such that the material adheres only to regions not originally covered by the mask such that the mask acts as a negative resist. Using such techniques, feature sizes of devices smaller than the smallest droplet printed may be fabricated.