Abstract: A graded junction termination extension in a silicon carbide (SiC) semiconductor device and method of its fabrication using ion implementation techniques is provided for high power devices. The properties of silicon carbide (SiC) make this wide band gap semiconductor a promising material for high power devices. This potential is demonstrated in various devices such as p-n diodes, Schottky diodes, bipolar junction transistors, thyristors, etc. These devices require adequate and affordable termination techniques to reduce leakage current and increase breakdown voltage in order to maximize power handling capabilities. The graded junction termination extension disclosed is effective, self-aligned, and simplifies the implementation process.

Abstract: A mold having a pattern of a concavo-convex surface including protrusion and recess is prepared and the pattern is transferred to a resist layer formed on a substrate by an imprinting method. The side surface of a protrusion of the transferred resist pattern is then etched so that the protrusion has a width narrower than a width of the corresponding recess formed to the mold. This resist pattern forming method is preferably applicable to a magnetic recording medium manufacturing method and a magnetic head manufacturing method.

Abstract: The present invention discloses a technique of removing a substance from a substrate surface, such as stripping photoresist from a wafer, or forming a substance on a substrate surface. Substrates to be treated are parallel arranged at an equal interval and are immersed in a liquid with only a lower portion thereof being below the liquid surface. Gas such as ozone is introduced into the liquid and is continuously bubbling below the substrates. The bubbles will ascend between two adjacent substrates and climb on the surfaces of the substrates before they burst. The liquid boundary layers on the substrate surfaces are compressed and refreshed in the course of a dragging ascent of the bubbles, enhancing mass transfer between gas/liquid/solid substances across the liquid boundary layer, thereby resulting in a fast reaction and a fast treatment of the surface of the substrates.

Abstract: A method of forming a micro pattern in a semiconductor device, wherein a first polysilicon film, a buffer oxide film, a second polysilicon film, an anti-polishing film, and a first oxide film are sequentially laminated on a semiconductor substrate having a to-be-etched layer. The first oxide film, the anti-polishing film and the second polysilicon film are patterned. After nitride film spacers are formed on the patterned lateral portions, a second oxide film is formed on the entire structure. A Chemical Mechanical Polishing (CMP) process is performed using the anti-polishing film as a stopper. Thereafter, after the nitride film spacers are removed, the second oxide film and the second polysilicon film are removed using a difference in etch selective ratio between the oxide film and the polysilicon film. A hard mask for forming a micro pattern having a structure in which the first polysilicon film and the buffer oxide film are laminated is formed.

Abstract: Novel interconnect structures possessing a OSG or polymeric-based (90 nm and beyond BEOL technologies) in which advanced plasma processing is utilized to reduce post lithographic CD non-uniformity (“line edge roughness”) in semiconductor devices. The novel interconnect structure has enhanced liner and seed conformality and is therefore capable of delivering improved device performance, functionality and reliability.

Abstract: A slurry composition useful for chemical mechanical polishing of the surface of a material layer, e.g., a silicon oxide layer, is disclosed. A first material surface which is exposed to the slurry exhibits hydrophilicity, while a second material layer, e.g., a polysilicon layer, the surface of which is also exposed to the slurry, exhibits hydrophobicity, and accordingly acts as a polishing stopping layer. The slurry composition consists essentially of water, abrasive grains, and a polymer additive having both hydrophilic and hydrophobic functional groups.

Abstract: The present invention relates to a method of manufacturing semiconductor device with composite buffer layers. The method includes etching grooves in n type and p type semiconductor wafers respectively. The areas of grooves in n type wafer just correspond to the areas without grooves in p type wafer, and vice versa. The grooves in both n type and p type wafers have the same depth. Two wafers are directly bonded together so that the grooves in one wafer are filled with the grooves in the other wafer. Then, chemical bonding is implemented. The bonding may also be made through thin dielectric layer (e.g. SiO2). If necessary, grinding, polishing or chemical mechanical polishing processes are carried out to remove the redundant material. Thereby, it is easy to manufacture the semiconductor device with composite buffer layer as voltage sustaining layer.

Abstract: A stopper for chemical mechanical planarization comprising an organosilicon polymer, in particular a polycarbosilane, is provided. The stopper used for polishing wafers with a wiring pattern in the manufacture of semiconductor devices to protect interlayer dielectric films made of a material such as SiO2, fluorine dope SiO2, or organic or inorganic SOG (Spin-on glass) from damages during the chemical mechanical planarization process.

Abstract: Fabricating a semiconductor includes depositing a metal layer outwardly from a dielectric layer and forming a mask layer outwardly from a first portion of the metal layer. Atoms are incorporated into an exposed second portion of the metal layer to form a composition-altered portion of the metal layer. The mask layer is removed from the first portion of the metal layer and a barrier layer is deposited outwardly from the metal layer. A poly-Si layer is deposited outwardly from the barrier layer to form a semiconductor layer, where the barrier layer substantially prevents reaction of the metal layer with the poly-Si layer. The semiconductor layer is etched to form gate stacks, where each gate stack operates according to one of a plurality of work functions.

Abstract: A chemical mechanical polishing pad. The pad contains a water-insoluble matrix and Water-soluble particles dispersed in the water-insoluble matrix material and has a polishing surface and a non-polishing surface on a side opposite to the polishing surface. The pad has a light transmitting area which optically communicates from the polishing surface to the non-polishing surface. The non-polishing surface of the light transmitting area has a surface roughness (Ra) of 10 pm or less.

Abstract: In a method for manufacturing a multi-thickness gate dielectric layer of a semiconductor device, a first dielectric layer is formed on a semiconductor substrate. A second dielectric layer is formed using a different dielectric material from the material constituting the first dielectric layer on the first dielectric layer. A portion of the second dielectric layer is selectively removed so as to selectively expose the first dielectric layer under the second dielectric layer. A portion of the exposed first dielectric layer is selectively removed so as to selectively expose the semiconductor substrate under the exposed first dielectric layer. Thereafter, a third dielectric layer having a thinner thickness than the first dielectric layer is formed on the exposed semiconductor substrate.

Abstract: A porous low-k film, a sacrificial film that can be dissolved in a pure water, an antireflection film and a resist film are successively formed on a dielectric film on a wafer and subsequently exposing the resist film to light in a prescribed pattern and developing the resist film so as to form a prescribed circuit pattern in the resist film. Then, the wafer W is etched so as to form a via hole in the porous low-k film, followed by processing the wafer with a hydrogen peroxide solution so as to denature the resist film. Further, the sacrificial film is dissolved in a pure water so as to strip the resist film and the antireflection film from the water. As a result, a via hole excellent in the accuracy of the shape is formed without doing damage to the dielectric film.

Abstract: A system and method is disclosed for selectively increasing a wet etch rate of a large raised area portion of a semiconductor wafer with respect to a wet etch rate of a small raised area portion of the semiconductor wafer. A resist mask on the semiconductor wafer is etched to create a large via over the large raised area portion and a small via over the small raised area portion. An ion implantation beam is applied with an impact direction that enables ions to pass through the large via but does not enable ions to pass through the small via. The ions that pass through the large via increase the wet etch rate of the underlying portion of the semiconductor wafer. In one embodiment the impact direction has a tilt angle of forty five degrees and a rotation angle of forty five degrees.

Abstract: The invention provides a laser etching method for optical ablation working by irradiating a work article formed of an inorganic material with a laser light from a laser oscillator capable of emitting in succession light pulses of a large energy density in space and time with a pulse radiation time not exceeding 1 picosecond, wherein, in laser etching of the work article formed of the inorganic material by irradiation thereof with the laser light from the laser oscillator with a predetermined pattern and with a predetermined energy density, there is utilized means for preventing deposition of a work by-product around the etching position.

Abstract: A method of plasma etching, in particular of anisotropic plasma etching, of laterally defined structures in a silicon substrate, using a process gas, includes having at least one passivating material precipitated on the side walls of the laterally defined structures at least from time to time prior to and/or during etching. In an exemplary method, at least one of the compounds selected from the group ClF3, BrF3, or IF5 is added to the process gas as a fluorine-delivering etching gas. In another exemplary method, NF3 is added to the process gas, at least from time to time, as an additive consuming the passivating material. Finally, in another exemplary method, a light and easily ionizable gas, in particular H2, He, or Ne, is added, at least from time to time, to the process gas. The three exemplary methods may be combined.

Abstract: After forming a gate insulating film on a semiconductor substrate, a silicon film is deposited on the gate insulating film, and a high-melting point metal film is deposited on the silicon film. After forming a hard mask made of a silicon oxide film or a silicon nitride film on the high-melting point metal film, the high-melting point metal film is dry etched by using the hard mask as a mask. After removing a residue or a natural oxide film present on the silicon film through dry etching, the silicon film is dry etched by using the hard mask as a mask. The residue or the natural oxide film is removed while suppressing excessive etching of the silicon film.

Abstract: A method for fabricating a microelectronic fabrication employs an undoped silicate glass layer as an etch stop layer when etching a doped silicate glass layer with an anhydrous hydrofluoric acid etchant. The method is particularly useful for forming a patterned salicide blocking dielectric layer when fabricating a complementary metal oxide semiconductor device.

Abstract: A solution and method is described for etching TaN, TiN, Cu, FSG, TEOS, and SiN on a silicon substrate in silicon device processing. The solution is formed by combining HF at 49% concentration with H2O2 at 29%–30% concentration in deionized water.

Abstract: Methods and apparatuses for removing material from a microfeature workpiece are disclosed. In one embodiment, the microfeature workpiece is contacted with a polishing surface of a polishing medium, and is placed in electrical communication with first and second electrodes, at least one of which is spaced apart from the workpiece. A polishing liquid is disposed between the polishing surface and the workpiece and at least one of the workpiece and the polishing surface is moved relative to the other. Material is removed from the microfeature workpiece and at least a portion of the polishing liquid is passed through at least one recess in the polishing surface so that a gap in the polishing liquid is located between the microfeature workpiece and the surface of the recess facing toward the microfeature workpiece.

Abstract: Polysilicon lines are formed, featuring an upper portion extending beyond the lower portion that defines the required CD. Accordingly, metal silicide layers of increased dimensions can be formed on the upper portion of the polysilicon lines so that the resulting gate structures exhibit a very low final sheet resistance. Moreover, in situ sidewall spacers are realized during the process for forming the polysilicon lines and without additional steps and/or costs.

Abstract: A method of producing prepolymeric materials from lignin is disclosed. The method uses lignin which has been hydroxyalkyl modified, such that the lignin is substantially non-phenolic and solvent soluble and/or liquid. The modified lignin is reacted with materials which yield prepolymers which may be polymerized according to known methods to produce useful polymers.