Abstract: Cascaded programmable logic arrays are used to program any type of flip-flop. The latch itself can be embedded in the array when using cascaded PLA's. The arrays can be cascaded to provide logic functions using less total area than a single array embodying the same function.

Abstract: A MOSFET sense amplifier applies both input signals to both input transistors of a common-gate sense amplifier; each input signal being applied to the source of one input transistor and the gate of the other, thereby effectively doubling the applied input signal.

Abstract: A stable sense rail amplifier for CMOS memories is provided allowing very small voltage swings at or very close to the power supply rail to be transformed into substantially rail-to-rail swings. The input of the amplifier is coupled to the output of memory cells which may be designed to have output swings of 200 millivolts or less. These output swings are shifted to approximately the center of the range between the supply voltage and ground. While the level shifting is performed a small amount of linear gain is added. Subsequently the shifted signal is applied to a linear high gain amplifier stage. The high gain amplifier has as its output a substantially rail-to-rail signal. The total delay from the input rail of the amplifier to the high gain inverting amplifier stage is limited to the transfer time of a single CMOS FET. The amplifier is self-biasing and self-referencing.

Abstract: The invention provides an inverting amplifier having a CMOS inverter and a MOSFET, the latter being connected to an input-output path of the CMOS inverter to autozero the CMOS inverter to its toggle point upon being turned on. An output signal from a CMOS inverter which has a short-circuited input-output path is supplied to the back gate of the MOSFET. Even if a gate threshold voltage of the MOSFET varies, its ON resistance is kept substantially constant.

Abstract: A logic circuit (FIGS. 4A, 5A and 6A) comprises a current switch circuit (FIG. 4A) which has a non-threshold transfer characteristic (FIG. 4B), operates in non-saturation region, and is suited to a high speed operation.The current switch circuit is formed by a pair of transistors (6 or 7, and 8), one of which (6 or 7) receives an input signal at its base, and the other (8) has its base and collector connected in d.c. coupling to each other. The pair of transistors are connected with a common constant current source (9) at their emitters, deliver an output from their collectors, and are so biased as to operate in the non-saturation region.In the current switch circuit, due to the d.c. coupling between the base and the collector of the other transistor (8), the voltage level of the collector changes linearly in accordance with the input signal of the current switch circuit. This allows for a transfer characteristic having no threshold and a very small delay time between the input signal and the output signal.

Abstract: A programmable logic array includes a plurality of MOS switching devices formed at preselected locations in an array made up of input and output lines and intersecting product term lines. One group of MOS devices constituting the "AND" plane arranged at the intersections of the input lines and product term lines performs a logic operation on input signals to the array and outputs logic signals onto the product term lines. A second group of MOS devices constituting the "OR" plane located at the intersections of the output lines and product term lines receives the outputs of the "AND" plane devices and performs a logic operation on those signals to produce a set of output signals that are presented at the outputs of the array for use by an external device. The merged plane array of the invention advantageously includes dual-gate MOS devices as switching elements to reduce the capacitance on the product term lines and output lines and thereby to increase the operating speed of the array.

Abstract: Each chip of a microprocessor chipset is synchronized by an associated controller which adjusts a control signal for controlling the delay of a variable delay circuit during each operating cycle. The controller tailors the control signal for each chip by an op-amp which compares the output of an internal clock in each chip with a reference system clock.

Abstract: In the field of large-scale-integrated digital GaAs circuits, a high-entrance high-speed logical operator utilizing so-called "quasi-normally-off" Schottky-gate field-effect transistors (MESFETS) having a low threshold voltage. By means of a single very-high-speed logic gate, the operator thus performs AND - NAND - OR functions by utilizing in an input branch a saturable resistive load in series with a pair of quasi-normally-off MESFET's each having a maximum of two Schottky gates, the drains of the transistors being connected to an output transistor of the same type. Two identical portions of circuit are mounted in parallel with an output half-branch comprising a diode in series with another saturable resistive load.

Abstract: The device comprises a capacitor, first means for taking into account, in logic form, the potential of the capacitor, second means which, in a first time, fixes the potential of the capacitor to a given value, third means which, in a second time, modify or do not modify the potential of the capacitor, depending on whether or not the charge quantity to be detected is present or absent, and fourth means which, in a third time, reloop the output of the first means to the input of the first means, the output of the first means constituting the output of the detection and storage device.Application to digitally programmable filters.

Abstract: In a circuit arrangement constructed in accordance with ECL technology, having an input emitter follower, a differential amplifier and an output emitter follower for the non-inverted output signal, the emitter of the transistor operated as an output emitter follower is connected to the collector of the transistor operated as an input emitter follower. This provides not only an elimination of stray power consumption but, rather, also enables the potential of the output to be increased far above the normal operating level by applying a potential to the input which is positive in comparison to the collector supply potential. Given use of the invention as input stages of programmable logic arrays, the same is of particular advantage in testing such arrays.

Abstract: A charge pump for providing programming voltages to the word lines of a semiconductor memory array is disclosed. The charge pump, configured as a combination of enhancement and native MOS transistors, prevents DC current from flowing from the source of the programming voltage to ground through unselected word lines, and thereby permits the design of semiconductor programmable memory arrays having on-chip programming voltage generation, allowing for design of semiconductor programmable memory arrays which operate from a single voltage power supply.

Abstract: A linear array of bistable data latches and logic gates arranged to count the binary transitions, both low to high and high to low, of a clock signal and provide a threshold style output code, characterized along the array by high logic states on one side of the threshold point and low logic states on the opposite side. Each latch in the array is permitted to set when a clock transition occurs after the preceding latch has set or to reset when a clock transition occurs after the succeeding latch has reset. Clock phasing and count enable/disable logic may be included along with direct set/reset inputs in order to accomplish parallel and/or ripple preset/clear functions or other output code modifications.

Abstract: An amplifier circuit for sensing and refreshing stored information, utilized with a voltage supply. The amplifier is of the type that is capable of assuming first and second conditions in response to signals at first and second input nodes. The circuit comprises first and second cross coupled devices each capable of assuming a high and low conduction state. Restore circuitry means is provided connected between the active devices and the voltage supply for selectively connecting the supply solely to the device assuming a low conduction state. In a dynamic random access memory embodiment means is further provided for alternately precharging the nodes to a predetermined state and applying stored information to the nodes to cause the amplifier to assume first and second conditions in response to stored information.

Abstract: This disclosure relates to a programmable logic array having an AND array disposed for receiving n input signals, an OR array providing k output signals on k output lines and m term lines coupling the AND and OR arrays together. New and improved AND and OR arrays are disclosed wherein the AND array includes n X m cells and each cell has first and second transistor means coupled in series between one of the term lines and a reference potential. Each cell includes a storage element that has an output terminal coupled to the control element of the first transistor means and one of the n input terminals is coupled to the control element of the second transistor means. The OR array includes m X k cells wherein each cell has third and fourth transistor means coupled in series between one of said output lines and a reference potential.

Abstract: A series circuit consisting of the emitter-collector path of a first transistor of npn type and an input current source is connected between a negative voltage source and a positive voltage source. Another series circuit consisting of the emitter-collector path of a second transistor of npn type and the collector-emitter path of a fourth transistor of pnp type is also connected between the negative and positive voltage sources. A further series circuit consisting of a first resistor, the emitter-collector path of a third transistor of npn type, a second resistor, and the collector-emitter path of a fifth transistor of pnp type is connected between the negative and positive voltage sources. The second and third transistors have their bases connected together. The fourth and fifth transistors have their bases connected together. The collector of the first transistor is connected to the base of the fifth transistor. The base of the first transistor is connected to the emitter of the sixth transistor.

Abstract: A high speed logic latching circuit consists of a pair of inverters and feedback switches used to latch the inverters. A pair of input switching means allows data to enter the latch when the latch is disabled. This configuration allows for high speed, reduced substrate area and true complementary outputs.

Abstract: An address buffer circuit is provided which has first and second MOS transistors whose current paths are connected in series with each other and whose gates are supplied with input signals of opposite phases, and third and fourth MOS transistors whose current paths are connected in series with each other. The first and third MOS transistors are of I-type. The gate of the third MOS transistor is connected to a junction of the first and second MOS transistors and the gates of the second and fourth MOS transistors are commonly connected. The address buffer circuit further has a MOS transistor which controls the conduction state of the third MOS transistor in response to an external control signal.

Abstract: A sense amplifier circuit used in, for example, a MIS static RAM includes a differential amplifier (Q.sub.11 through Q.sub.14) for sensing and amplifying the difference in potential between two input lines (DB and DB) and generating two bipolar differential signals (D and D) and a pull-down circuit (Q.sub.15) for establishing a reference potential (V.sub.REF) for the differential amplifier. A compensation circuit (Q.sub.16, Q.sub.17 and Q.sub.18) is provided for detecting the in-phase component of the input lines so as to control the pull-down circuit. Therefore, the fluctuation of the reference potential follows the fluctuation of the in-phase component of the input lines so that a stable and high-speed sensing operation is effected.

Abstract: A semiconductor device comprising a substrate voltage-generating circuit which has an oscillating circuit and a pumping circuit. The substrate voltage-generating circuit also has a control circuit for controlling the application of the output signal of the oscillating circuit to the pumping circuit and a terminal electrode for receiving an external signal to control the control circuit and to stop the application of the output signal of the oscillating circuit to the pumping circuit.

Abstract: A power up reset pulse generator circuit provides a reset pulse to initialize the states of logic elements in a low power field effect transistor (FET) integrated circuit. The reset pulse generator includes a pair of P-channel enhancement FETs and a first capacitor connected in a series charging path between V.sub.DD and V.sub.SS power supply terminals of the integrated circuit. A second capacitor, and a pair of N-channel enhancement FETs are connected in a second series charging path between the V.sub.DD and V.sub.SS terminals. The second capacitor is connected between the V.sub.DD terminal and an output node, at which the reset pulse is provided. Before power is applied, the first and second capacitors are uncharged and all four FETs are off. When power is applied and the potential between V.sub.DD and V.sub.SS terminals exceeds twice the P-channel threshold voltage, the P-channel FETs turn on, thereby allowing the first capacitor to begin charging. In the meantime, the voltage at the output has followed V.