Abstract: An input circuit is provided for converting an ECL level to a CMOS level. The input circuit of the invention includes a first input circuit having at least a P-type MOSFET and an N-type MOSFET connected in series. The gate of the P-type MOSFET is connected to the input of the circuit for receiving an input signal of the ECL level and the output of the circuit is taken out from between both MOSFETs. A voltage generation circuit is also provided for applying a voltage to the gate of the N-type MOSFET of the first input circuit to control the logic threshold voltage of the first input circuit. The voltage generation circuit includes a second circuit, which receives a logic threshold voltage of ECL as its input and is equivalent to the first input circuit, and an amplification circuit of at least one stage which receives the output of the second input circuit and the logic threshold voltage of CMOS as its input and amplifies the difference between them.

Abstract: A CMOS bistable circuit is employed as an address buffer or latch for a semiconductor memory or the like. The circuit includes a pair of differential gated inputs, one from an address terminal, and the other from a reference voltage. The same clock used to gate the inputs also preconditions the circuit to be in a balanced status, and holds off conduction of any transistor in the circuit. In this manner, a circuit of high speed, low power, and minimum complexity is provided.

Abstract: A charge coupled device (CCD) with separately addressable input signal gates is operated in the potential equilibrium mode. With properly selected voltage potentials the CCD can be used as a high speed linear detector of a variable analog signal without the need of preceeding independent sample and hold or peak detector circuits. The result is the efficient minimum/maximum detection of an analog signal in a fast-in/slow-out digitizer.

Abstract: An active pulldown means is provided for the output line of an ECL gate. The pulldown means utilizes a Wilson current mirror as a differential-to-single ended converter in a transition detection arrangement which tracks temperature variations and rejects supply voltage transients in order to ensure correct operation under all conditions. The desired and the present output conditions are compared in the detection scheme. High transient current is supplied to the output only when the two output conditions do not match for output high-to-low transitions.

Abstract: The operating potential to an amplifying section is selectively altered to cause the stages of the amplifying section to operate in the voltage follower mode during one time period and as inverters during another, succeeding time period. A selectively enabled preamplifier adapted to receive small signals which are offset with respect to the voltage rail level and which produces at its outputs, signals which tend to be centered about the midpoint of the operating potential is coupled to the amplifying section to control its gain during certain portions of the amplifying section operation.

Abstract: A flip-flop type sense amplifier for a semiconductor memory device is disclosed, the sense amplifier comprising a pair of CMOS inverters cross-coupled with each other to form a CMOS flip-flop circuit having a pair of buffer circuits, for receiving the read-out voltage signals from multi-level memory cells and a predetermined reference voltage, respectively, and a pair of switching circuits for inverting a power source voltage across the flip-flop circuit through common sources of the flip-flop circuit, in response to the transition between a stand-by sequence and a latching operating. The common source of the p-channel transistors of the CMOS flip-flop circuit is connected to a negative potential source, and the common source of the n-channel transistors is connected to a positive potential source during a stand-by sequence, and vice versa, during a latching operation. This unique potential supply method enhances operational speed of the sense amplifier.

Abstract: Disclosed is a complementary MOSFET logic circuit having a complementary MOS inverter with a pregiven ratio of the channel widths of a P channel MOSFET and an N channel MOSFET and pregiven threshold voltages of the FETs so as to have an input voltage characteristic adapted to an output voltage characteristic, and a buffer circuit which includes a bipolar transistor for receiving at the base thereof a signal from the output terminal of the complementary MOS inverter and an N channel MOSFET for receiving at the gate thereof an input signal applied to the complementary MOS inverter. The inverter and buffer are connected in series to one another between a high potential applying point and a low potential applying point, and a signal corresponding to a logic output signal of the complementary MOS inverter is produced at the output terminal thereof.

Abstract: An interface circuit to couple logic signals from a logic gate of one kind of logic family to a logic gate of another operating at different logic state voltages, where a latch circuit is used with the first of two cascaded inverters to provide the desired interface circuit signal characteristics. One inverter is provided with a supply reduction threshold means as is another inverter in the latch so that the two inverters perform substantially similarly to one another. The latch allows independent adjustments of opposite direction logic level transitions to provide a desired noise margin.

Abstract: A buffer input circuit, such as for use with a TTL level input, includes an additional or dummy input buffer stage in which the MOS devices are scaled and configured as in a real input buffer stage. The current produced in the dummy input buffer stage for an input voltage at a preset minimum high level is sensed and converted to a compensation voltage, which is applied to the real buffer stages, thereby to modify the current in the real buffer stages to a desired minimum level.

Abstract: A charge transfer device having a plurality of transfer gates to which phased clock pulses are provided to transfer charge serially from semiconductor regions underlying the transfer gates through an output region underlying an output gate to a charge detector region. The last transfer gate preceding the output gate is fed with a phased clock pulse via a signal line other than the signal lines feeding the remaining transfer gates. The former signal line has an RO time constant lower than that for the other signal lines and permits rapid charge transfer from the last stage to the charge detecting device.

Abstract: A sense amplifier for a computer memory includes a plural stage differential amplifier. The first stage of the differential amplifier includes an input emitter follower connected to the input of the first stage differential pair. A negative feedback loop is connected around the first stage. The negative feedback loop enhances the response characteristic of the amplifier. Circuit means are also provided which enables the selective steering of energizing current through or away from the second stage of the differential amplifier to provide for the selective blocking of the output of the sense amplifier.

Abstract: A PMOS input buffer compatible with logic voltage levels provided by NMOS or TTL microprocessor means uses a limited number of transistors of limited size for driving a load in response to such logic and is adapted for use under widely varying operating conditions.

Abstract: A four layer insulated gate controlled semiconductor device has a range of anode-cathode currents over which gate control potentials will extinguish such anode-cathode current. Coupling circuitry for limiting the rate of change of turn-off gate control potential to the gate of the device enhances the range of anode-cathode current over which control is maintained.

Abstract: A sense amplifier is coupled to a pair of bit lines for detecting and amplifying a voltage differential therebetween. The sense amplifier has a first differential amplifier coupled to the pair of bit lines enabled in response to a first signal. The sense amplifier also has a second differential amplifier coupled to the pair of bit lines which is enabled a predetermined time duration following the occurrence of the first signal.

Abstract: The invention relates to an integrated voltage-current converter circuit for generating a current which produces a voltage drop across a reference resistor, which voltage drop is determined by an input voltage. In order to compensate for the spread in width of the reference resistor formed in the integrated circuit, this reference resistor is formed by two parallel-connected resistors having the same resistance per unit area, the same length and different widths, and the compensated output current is formed by the difference between the currents which flows through these resistors.

Abstract: A semiconductor circuit and method for comparing an input signal voltage level against the circuit's supply voltage level and for providing a corresponding binary output signal, the circuit comprising first and second semiconductor devices for establishing voltage levels corresponding to the compared voltage levels on first and second nodes, respectively, third, fourth, fifth, and sixth semiconductor devices in combination with third, fourth, and fifth nodes arranged and connected to operate as a bistable element which is predisposed during a first time interval to favor one of the binary states in response to the difference in voltage levels established on the first and second nodes, and through the action of a seventh semiconductor device, which switches the main conductive path through the circuit off during the first interval and on during a second time interval, effecting a regenerative toggling of the bistable element to the favored state during the second time interval causing the desired binary signal

Abstract: A device for generating a variable and adjustable control signal is provided. The device is of the type in which the control signal is generated in response to the manipulation of the device by an operator and is applied to suitable controlled amplifiers such as voltage controlled amplifiers or filters. The device comprises variable voltage generating member and a holding circuit coupled thereto. The voltage generating member is capable of delivering a voltage corresponding to the location where the operator touches or presses and when the voltage generating member is not touched the voltage generating member is inhibited from delivering a voltage. The holding circuit delivers a first signal corresponding to the voltage delivered under the manipulation of the voltage generating member, and holds a voltage corresponding to the previously manipulated location and delivers a second signal corresponding to the held voltage during the time the voltage generating member is not manipulated.

Abstract: An improved sense amplifier circuit for sensing information in the cells of a semiconductor memory device is presented. The sense amplifier circuit as presented includes AC-coupled positive feedback means to provide a reduction in sensing delay time, and thus, faster memory access time.

Abstract: A dynamic re-programmable logic array is disclosed which has an AND array disposed for receiving n input signals, an OR array providing k output signals on k output lines and m term lines and m bit lines coupling the AND and OR arrays, wherein the array comprises new and improved random access AND and OR arrays incorporating programmable charge storage elements. Refresh logic is also provided for periodically restoring the charge programmed on the charge storage elements.

Abstract: A digital synchronizer circuit including an input to receive an asynchronous level and a second input to receive an ansynchronous pulse. Both inputs are connected to the synchronizer input circuitry which will provide a level output for either type of input signal. This circuitry is connected to the remainder of the digital synchronizer which includes a latch connected to the level input and a level sensitive circuit connected to the output of the latch. The latch is constructed to provide a rapid transition between a logic "0" and "1". In addition, the latch is periodically cleared. The level sensitive circuit provides a propagation barrier to any metastable state that may be present in the latch. However, the level sensitive circuit is also constructed for rapid transition from a logic "0" to a logic "1" when such a state occurs within the latch. An additional latch is connected in a further embodiment to provide additional reliability of the synchronizer circuit.