Abstract: A display substrate and a manufacturing method thereof. The display substrate includes a display region, a barrier region and an opening region, the barrier region is located between the display region and the opening region. The barrier region includes a first barrier wall, a first barrier wall, and a second barrier wall which are sequentially arranged from the display region to the opening region. The first barrier wall includes a first metal layer structure, at least one lateral surface of the first metal layer structure surrounding the opening region is provided with a notch; the first intercepting wall includes a first insulating layer structure; the second barrier wall includes a second metal layer structure and a first stacked structure, at least one lateral surface of the second metal layer structure surrounding the opening region is provided with a notch.

Abstract: A display device includes a metal layer between a pixel-defining layer and an opposite electrode, the metal layer contacting the opposite electrode. The display device includes subpixels disposed on a substrate. The sub-pixels each include a pixel electrode, an opposite electrode facing the pixel electrode, an emission layer disposed between the pixel electrode and the opposite electrode, a pixel-defining layer surrounding the emission layer. The display device includes a metal layer disposed between the pixel-defining layer and the opposite electrode, the metal layer contacting the opposite electrode.

Abstract: A display apparatus including: a first thin-film transistor and a second thin-film transistor on a substrate, wherein the first thin-film transistor includes a first electrode layer, and the second thin-film transistor includes a second electrode layer; an insulating layer having a first contact hole and a second contact hole respectively exposing the first electrode layer and the second electrode layer; a first pixel electrode connected to the first thin-film transistor through the first contact hole; and a second pixel electrode connected to the second thin-film transistor through the second contact hole. A top surface of the first pixel electrode overlapping the first electrode layer in the first contact hole has a first step facing a first direction, and a top surface of the second pixel electrode overlapping the second electrode layer in the second contact hole has a second step facing a second direction opposite to the first direction.

Abstract: A semiconductor apparatus includes an element substrate including an effective pixel region having a plurality of effective pixels on one principal surface side of a first substrate, and a peripheral region positioned around the effective pixel region, a second substrate, and a first and a second bonding member configured to bond the both substrates. The second bonding member includes a material different from that of the first bonding member. In a planar view with respect to the one principal surface, the second substrate is disposed within the element substrate. The first bonding member is provided between the peripheral region and the second substrate. The second bonding member is provided between the effective pixel region and the second substrate. In a planar view with respect to the one principal surface, at least a part of an end portion of the second substrate is positioned on the first bonding member.

Abstract: A chip on film package includes a base film, a patterned circuit layer, a chip and a reinforcing sheet. The base film includes a first surface, a second surface opposite to the first surface and a mounting region located on the first surface. The patterned circuit layer is disposed on the first surface. The chip is mounted on the mounting region and electrically connected to the patterned circuit layer. The reinforcing sheet is disposed on the first surface and/or the second surface and exposes the chip, wherein a flexibility of the reinforcing sheet is substantially equal to or greater than a flexibility of the base film.

Abstract: A display device includes a substrate having a top surface, a bottom surface, and a first contact hole passing through the top surface and the bottom surface; a thin film transistor disposed above the top surface and including a semiconductor layer; a display element connected to the thin film transistor; a top conductive pattern disposed between the substrate and the thin film transistor and overlapping the semiconductor layer of the thin film transistor; a bottom conductive pattern disposed on the bottom surface and connected to the top conductive pattern through the first contact hole; and a bottom planarization layer disposed on the bottom surface, the bottom planarization layer disposed on the bottom conductive pattern.

Abstract: A display device includes a substrate including a display area in which a display element is arranged and a non-display area having a pad area outside the display area, a first thin-film transistor arranged in the display area of the substrate and including a first semiconductor layer and a first gate electrode insulated from the first semiconductor layer, a first voltage line which extends in a first direction on the first gate electrode, a data line apart from the first voltage line and which extends in the first direction, connection lines which connects the data line to a pad in the pad area in the display area, and a conductive layer arranged in a layer between the first voltage line and the data line.

Abstract: Techniques for forming a metastable phosphorous P-doped silicon Si source drain contacts are provided. In one aspect, a method for forming n-type source and drain contacts includes the steps of: forming a transistor on a substrate; depositing a dielectric over the transistor; forming contact trenches in the dielectric that extend down to source and drain regions of the transistor; forming an epitaxial material in the contact trenches on the source and drain regions; implanting P into the epitaxial material to form an amorphous P-doped layer; and annealing the amorphous P-doped layer under conditions sufficient to form a crystalline P-doped layer having a homogenous phosphorous concentration that is greater than about 1.5×1021 atoms per cubic centimeter (at./cm3). Transistor devices are also provided utilizing the present P-doped Si source and drain contacts.

Abstract: A memory element and methods of constructing the memory element are described. The memory element may include a bottom electrode structure having an uppermost portion of a first dimension. The memory element may further include a MTJ pillar having a bottommost portion forming an interface with the uppermost portion of the bottom electrode structure. The bottommost portion of the MTJ pillar may have a second dimension that is less than the first dimension. The memory element may further include oxidized metal particles located on an outermost sidewall of the MTJ pillar. The memory element may further include a top electrode structure located in the MTJ pillar.

Abstract: In micromechanical pressure sensor device and a corresponding production method, the micromechanical pressure sensor device is provided with a first diaphragm; an adjacent first cavity; a first deformation detection device situated in and/or on the first diaphragm for detecting a deformation of the first diaphragm as a consequence of an applied external pressure change and as a consequence of an internal mechanical deformation of the pressure sensor device; a second diaphragm; an adjacent second cavity; and a second deformation detection device situated in and/or on the second diaphragm for detecting a deformation of the second diaphragm as a consequence of the internal mechanical deformation of the pressure sensor device, where the second diaphragm is developed in such a way that it is not deformable as a consequence of the external pressure change.

Abstract: A light-emitting element having high emission efficiency which includes a fluorescent material as a light-emitting substance is provided. A light-emitting element includes a pair of electrodes and an EL layer between the pair of electrodes. The EL layer includes a light-emitting layer. The light-emitting layer includes a host material and a guest material. The host material has a difference of more than 0 eV and less than or equal to 0.2 eV between a singlet excitation energy level and a triplet excitation energy level. The guest material is capable of emitting fluorescence. The triplet excitation energy level of the host material is higher than a triplet excitation energy level of the guest material.

Abstract: The present application provides a display panel and a display device. The display panel includes a substrate, a driving circuit layer disposed on the substrate, and a light-emitting layer disposed on the driving circuit layer. The driving circuit layer includes a first metal layer, the first metal layer includes a first metal trace, the light-emitting layer includes multiple light-emitting portions, and a vertical distance between an orthographic projection of a center of each light-emitting portion projected on the first metal layer and a symmetry axis of the first metal trace is less than or equal to 5 ?m.

Abstract: An array substrate, a display panel, and a display device are provided. The array substrate includes a substrate, a semiconductor layer, a gate insulation layer, a gate layer, an interlayer insulation layer, and data lines, wherein the semiconductor layer is directly below the data lines.

Abstract: A first metal layer, an inorganic insulating film, and a second metal layer are provided. A first wiring line led to a peripheral edge of a cutout portion is provided in the first metal layer. A second wiring line led to the peripheral edge of the cutout portion is provided in the second metal layer. The first lead wiring line and the second lead wiring line overlap each other through intermediation of the inorganic insulating film.

Abstract: An OLED display panel and a manufacturing method thereof, and an OLED display device are disclosed. The OLED display panel includes a base substrate; a first film layer and a second film layer, sequentially provided on the base substrate, a first via-hole penetrating through the first film layer being provided in the first film layer, a second via-hole penetrating through the second film layer being provided in the second film layer at a position corresponding to the first via-hole, the second via-hole being in communication with the first via-hole, and the first film layer and the second film layer form a first step at a position of the second via-hole; and a connection wire, provided in both the first via-hole and the second via-hole and overlying the first step.

Abstract: An array substrate, an electroluminescent display panel, and a display device are disclosed. The array substrate includes: a base substrate, and a first signal line, an insulating layer and a second signal line provided sequentially on the base substrate in a direction perpendicular to the base substrate; wherein the first signal line has a first portion and a second portion, the first portion has a resistance higher than a resistance of the second portion, and at least a part of the first portion is overlapped with the second signal line, and the second portion is non-overlapped with the second signal line.

Abstract: A high frequency module includes a power amplifier and a substrate on which the power amplifier is mounted. The power amplifier includes a first external terminal and a second external terminal formed on a mounting surface. The substrate includes a first land electrode and a second land electrode formed on one principal surface. The first external terminal is connected to the first land electrode, and the second external terminal is connected to the second land electrode. A distance from the mounting surface to a connection surface of the first external terminal is shorter than a distance from the mounting surface to a connection surface of the second external terminal, and a distance from a connection surface of the first land electrode to the one principal surface is longer than a distance from a connection surface of the second land electrode to the one principal surface.

Abstract: A method includes forming first and second trenches in a semiconductor substrate. The method further includes filling the first and second trenches with polysilicon. The polysilicon is oppositely doped from the semiconductor substrate. A Schottky contact is formed on the semiconductor substrate between the first and second trenches. The method also includes forming an anode for the Schottky contact. The anode is coupled to the polysilicon in the first and second trenches.

Abstract: An organic light-emitting display apparatus includes a substrate, pixels, a pixel defining layer (PDL), a first via layer, a second via layer, first lines, and a second line. The pixels are arranged on the substrate in a first direction (D1) and a second direction (D2) intersecting one another, and include organic light-emitting diodes (OLEDs). The OLEDs include pixel electrodes (PEs). The PDL covers edges of the PEs and defines light-emitting regions via openings partially exposing the PEs. The first and second via layers are between the PEs and the substrate. The first lines extend in the D2 between the first via layer and the substrate. The second line is between the second and first via layers. The second line at least partially extends around the light-emitting regions. The second line contacts the first lines through via holes. Each via hole is provided every two pixels arranged in the D2.

Abstract: An organic light emitting diode display device including a substrate having a display region, a peripheral region around the display region, and a pad region located on one side of the peripheral region, a sub-pixel structure in the display region on the substrate, a plurality of fan-out wires on the substrate and located in the peripheral region, each one of the fan-out wires including a first diagonal portion, a first straight portion, and a second diagonal portion, a first sub-power supply wire on the fan-out wires and located in the peripheral region, and a first planarization layer on the first sub-power supply wire and having an opening configured to expose the first sub-power supply wire on a portion at which the first straight portion of each of the fan-out wires is located.