Abstract: Structures for a field-effect transistor and methods of forming a structure for a field-effect transistor. A sacrificial layer is epitaxially grown on a bulk semiconductor substrate, a plurality of epitaxial semiconductor layers are epitaxially grown over the sacrificial layer, and the sacrificial layer and the plurality of epitaxial semiconductor layers are patterned to form a fin. A first portion of the first sacrificial layer is removed to form a first cavity arranged between the plurality of epitaxial semiconductor layers and the bulk semiconductor substrate, and a first dielectric material is deposited in the first cavity. A second portion of the first sacrificial layer, which is located adjacent to the first dielectric material in the first cavity, is removed to form a second cavity between the first fin and the bulk semiconductor substrate. A second dielectric material is deposited in the second cavity.

Abstract: Techniques and mechanisms for forming a bond between wafers using a compliant layer. In an embodiment, a layer or layers of one or more compliant materials is provided on a first surface of a first wafer, and the one or more compliant layers are subsequently bonded to a second surface of a second wafer. The bonded wafers are heated to an elevated temperature at which a compliant layer exhibits non-elastic deformations to facilitate relaxation of stresses caused by wafer distortions. In another embodiment, a material of the compliant layer exhibits viscoelastic behavior at room temperature, wherein stress is mitigated by allowing wafer distortion to relax at room temperature.

Abstract: A light-emitting diode includes: a semiconductor epitaxial structure including a first semiconductor layer, a second semiconductor layer disposed over the first semiconductor layer, an active layer disposed between the first and second semiconductor layers; a first electrode electrically coupled to the first semiconductor layer; and a second electrode disposed over and electrically coupled to said second semiconductor layer; wherein: the first electrode includes a plurality of first sub-electrodes; the second electrode includes a plurality of second sub-electrodes; and any two adjacent first sub-electrodes and/or second sub-electrodes have a same projection distance.

Abstract: A light emitting apparatus (10) includes a substrate (100), an insulating layer (160), a light emitting element (102), a coating film (140), and a structure (150). The insulating layer (160) is formed over one surface of the substrate (100), and includes an opening (162). The light emitting element (102) is formed in the opening (162). The coating film (140) is formed over the one surface of the substrate (100), and covers a portion of the light emitting element (102), the insulating layer (160), and the one surface of the substrate (100). The coating film (140) does not cover another portion of the substrate (100) (for example, a portion of an end portion: hereinafter, referred to as a first portion). The structure (150) is located between the first portion of the substrate (100) and the insulating layer (160). The coating film (140) also covers the insulating layer (160).

Abstract: A synthetic resin molded article includes an electric element part extending in a distal direction and a primary molded part. The primary molded part has an element covering portion and a body portion. The element covering portion has a distal end surface exposed in the distal direction and a first side surface extending in a proximal direction opposite to the distal direction. The element covering portion covers a proximal portion of the electric element portion, and a distal end portion of the electric element portion projects from the distal end surface in the distal direction. The body portion has an intermediate surface exposed in the distal direction and a second side surface extending in the proximal direction. The body portion is disposed on a side of the element covering portion in the distal direction and is integrally connected to the element covering portion.

Abstract: The organic electroluminescence display device of an embodiment of the present invention includes a substrate, a plurality of pixels formed on the substrate, and a sealing film that covers the plurality of pixels. The sealing film includes a first barrier layer, a base layer covering the top surface of the first barrier layer, an inter layer locally formed on the top surface of the base layer, and a second barrier layer covering the top surface of the base layer and the top surface of the inter layer. The inter layer is formed so as to cover a step on the top surface of the base layer.

Abstract: A plurality of openings is formed in a dielectric layer formed on a semiconductor substrate. The plurality of openings comprises a first opening extending to the semiconductor substrate, a second opening extending to a first depth that is substantially less than a thickness of the dielectric layer, and a third opening extending to a second depth that is substantially greater than the first depth. A multi-layer gate electrode is formed in the first opening. A thin resistor structure is formed in the second opening, and a connection structure is formed in the third opening, by filling the second and third openings substantially simultaneously with a resistor metal.

Abstract: An EEPROM includes a floating gate transistor having a source region, a channel region and a drain region. A first capa implant zone on a drain-side of the floating gate transistor has a first dopant concentration level. A second capa implant zone in the first capa implant zone adjacent the drain region has a second dopant concentration level that is greater than the first dopant concentration level. A gate oxide region insulates the floating gate electrode from the channel region, first capa implant zone and second capa implant zone. A thickness of the gate oxide region is thinner at the second capa implant zone than at the channel region and first capa implant zone.

Abstract: Methods of forming a field-effect transistor and structures for a field effect-transistor. A sidewall spacer is formed adjacent to a sidewall of a gate structure of the field-effect transistor and a dielectric cap is formed over the gate structure and the sidewall spacer. A cut is formed that extends through the dielectric cap, the gate structure, and the sidewall spacer. After forming the cut, the sidewall spacer is removed from beneath the dielectric cap to define a cavity, and a dielectric material is deposited in the cut and in the cavity. The dielectric material encapsulates a portion of the cavity to define an airgap spacer.

Abstract: A method of fabricating a solar cell can include forming a dielectric region on a silicon substrate. The method can also include forming an emitter region over the dielectric region and forming a dopant region on a surface of the silicon substrate. In an embodiment, the method can include heating the silicon substrate at a temperature above 900 degrees Celsius to getter impurities to the emitter region and drive dopants from the dopant region to a portion of the silicon substrate.

Abstract: A manufacturing method of a flexible OLED panel, a flexible OLED panel, and a display is disclosed. The flexible OLED panel is manufactured by the manufacturing method, and the display includes the flexible OLED panel. The disclosure functions as a role of blocking crack diffusion by forming the opening holes in the inorganic layer to release the cracking stress; the opening holes are arranged in at least two rows, and two of the rows of the opening holes adjacent to each other are arranged in a dislocation manner in the surrounding direction so as to distribute at least one of the opening holes on a line connecting any position on the boundary of the second area away from the first area to any position of the display area, the diffusion of cracks at any position in the inorganic layer can be blocked by at least one of the opening holes.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to via structures and via patterning using oblique angle deposition processes. The method includes: depositing a material on a lower wiring layer; forming one or more openings in the material; filling the one or more openings with a conductive material; growing via structures on the conductive material; forming interlevel dielectric material on the via structures; and forming an upper wiring layer on the interlevel dielectric material and in contact with the via structures.

Abstract: Provided is a method of manufacturing a semiconductor device capable of dividing a wafer with metal formed on a rear surface thereof into individual pieces while suppressing chipping and defective cuts. The method of manufacturing a semiconductor device includes: forming a metal layer on a rear surface of a semiconductor substrate; performing blade dicing for the metal layer; and performing stealth Dicing® for the semiconductor substrate.

Abstract: An epitaxial substrate for semiconductor elements suppresses leakage current and has a high breakdown voltage. The epitaxial substrate for semiconductor elements includes: a semi-insulating free-standing substrate formed of GaN doped with Zn; a buffer layer formed of a group 13 nitride adjacent to the free-standing substrate; a channel layer formed of a group 13 nitride adjacent to the buffer layer; and a barrier layer formed of a group 13 nitride on an opposite side of the buffer layer with the channel layer therebetween, wherein part of a first region consisting of the free-standing substrate and the buffer layer is a second region containing Si at a concentration of 1×1017 cm?3 or more, and a minimum value of a concentration of Zn in the second region is 1×1017 cm?3.

Abstract: A flexible OLED display panel is disclosed and includes an encapsulation structure. The encapsulation structure includes: a first inorganic thin film formed on a surface of an OLED display layer and a surrounding region of the surface; a first organic thin film formed on a surface of the first inorganic thin film; and a plurality of dams. Each of the dams has a first sub-dam close to the first inorganic thin film and a second sub-dam away from the first inorganic thin film. A gap is formed between the first sub-dam and the second sub-dam which are located at a same side. The gap is filled with desiccant.

Abstract: A module can include a module card and first and second microelectronic elements having front surfaces facing a first surface of the module card. The module card can also have a second surface and a plurality of parallel exposed edge contacts adjacent an edge of at least one of the first and second surfaces for mating with corresponding contacts of a socket when the module is inserted in the socket. Each microelectronic element can be electrically connected to the module card. The front surface of the second microelectronic element can partially overlie a rear surface of the first microelectronic element and can be attached thereto.

Abstract: An acquisition system includes a processor, one or more sensors operatively coupled to the processor where the one or more sensors acquire at the ear, on the ear or within an ear canal, one or more of acceleration, blood oxygen saturation, blood pressure or heart-rate, and the one or more sensors configured to monitor a biological state or a physical motion or both for an event. The event can be a detection of a discrepancy when compared with a set of reference data by the one or more sensors or the biological state or the event can be one of a detection of an abrupt movement of a headset operatively coupled to the processor, a change in location of an earpiece operatively coupled the processor, a touching of the headset, a recognizing of a voice command, a starting or ending of a phone call, or a scheduled time.

Abstract: A technique relates to a semiconductor device. A bipolar transistor includes an emitter layer and a base layer, where the emitter layer and the base layer are doped with an impurity, the impurity being a same for the emitter and base layers. The bipolar transistor includes a collector layer.

Abstract: The present disclosure relates to a substrate structure with selective surface finishes used in flip chip assembly, and a process for making the same. The disclosed substrate structure includes a substrate body, a metal structure with a first finish area and a second finish area, a first surface finish, and a second surface finish. The metal structure is formed on a top surface of the substrate body, the first surface finish is formed over the first finish area of the metal structure, and the second surface finish is formed over the second finish area of the metal structure. The first surface finish is different from the second surface finish.

Abstract: Some embodiments include an integrated structure having a stack of alternating dielectric levels and conductive levels, vertically-stacked memory cells within the conductive levels, an insulative material over the stack and a select gate material over the insulative material. An opening extends through the select gate material, through the insulative material, and through the stack of alternating dielectric and conductive levels. A first region of the opening within the insulative material is wider along a cross-section than a second region of the opening within the select gate material, and is wider along the cross-section than a third region of the opening within the stack of alternating dielectric levels and conductive levels. Channel material is within the opening and adjacent the insulative material, the select gate material and the memory cells. Some embodiments include methods of forming vertically-stacked memory cells.