Abstract: A mixer circuit including a mixer, a voltage divider circuit, and an amplifier, is provided. The mixer receives a first input signal, a second input signal, and at least one set of bias voltages, and generates an output signal. A frequency of the output signal is related to a frequency of the first input signal and a frequency of the second input signal. The voltage divider circuit receives the bias voltages and generates a common mode signal at an output end. The amplifier is coupled to the mixer to receive the output signal, and is coupled to the output end of the voltage divider circuit and configured to suppress noise in the output signal, and generate a final output signal.

Abstract: A frequency multiplier includes an input section to receive a quadrature phase input signal having an input frequency, a mixer section coupled to the input section by a common mode node that forms a path for the common mode signal current to flow to the mixer section and magnetically coupled to the common mode node or capacitively coupled to the input section to generate a differential switching voltage at odd multiples of twice the input frequency, which switching voltage is applied to inputs of the mixer section, and an output section magnetically coupled to the mixer section, the output section being configured to generate an output voltage having a dominate frequency and sub-dominate frequencies spaced apart by the first multiple, the dominate frequency of the output voltage being a second multiple of the input frequency, where the second multiple is greater than the first multiple. Various arrangements are provided.

Abstract: A power-on reset signal generating device includes a reference voltage generator, a signal driver, and a stabilization circuit. The reference voltage generator generates a power-on reference voltage based on a voltage level of a power supply voltage. The signal driver drives the power-on reference voltage to generate a power-on reset signal. The stabilization circuit receives the power-on reset signal to keep a voltage level of the power-on reference voltage staying during a predetermined amount of time.

Abstract: A feedback control circuit in an LED driving circuit for driving a plurality of LED strings. Each LED string provides a headroom detecting voltage. The feedback control circuit has a status detecting circuit, a counting circuit and a modulating circuit. The status detecting circuit compares each headroom detecting voltage with a low headroom threshold voltage and a high headroom threshold voltage and generates an up self-status signal and a down self-status signal. The counting circuit counts or keeps unchanged and then generates a counting signal based on the up self-status signal and the down self-status signal. The modulating circuit generates a modulating signal based on the counting signal. And based on the modulating signal, the feedback control circuit generates a feedback control signal to regulate a bias voltage supplying the plurality of LED strings.

Abstract: Provided is a semiconductor device which can operate stably even in the case where a transistor thereof is a depletion transistor. The semiconductor device includes a first transistor for supplying a first potential to a first wiring, a second transistor for supplying a second potential to the first wiring, a third transistor for supplying a third potential at which the first transistor is turned on to a gate of the first transistor and stopping supplying the third potential, a fourth transistor for supplying the second potential to the gate of the first transistor, and a first circuit for generating a second signal obtained by offsetting a first signal. The second signal is input to a gate of the fourth transistor. The potential of a low level of the second signal is lower than the second potential.

Abstract: A power-on-reset (POR) circuit for CMOS logic is operable to transition between a POR_active state and a POR_inactive state and can include: (a) VDD/VT threshold circuitry to provide a Vtp_threshold voltage based on input Vdd and PMOS Vtp, and a Vtn_threshold voltage based on input Vdd and NMOS Vtn; (b) POR transition detect circuitry to provide a POR_transition signal (active/inactive) based on a function (Vtp, Vtn), which is a function of Vtp_threshold and Vtn_threshold; and (c) POR transition control circuitry to provide the POR_state signal (active/inactive) based on the POR_transition signal. For a POR out-of-reset transition, the POR transition detect circuitry to switch the POR_transition signal inactive based on the function (Vtp, Vtn) corresponding to the POR_inactive state, and the POR transition control circuitry, responsive to the POR_transition signal switching to inactive, to initiate a POR out-of-reset delay period, and to signal the POR_inactive state after the POR out-of-reset delay period.

Abstract: A bias circuit includes first and second bipolar transistors, first and second field-effect transistors, and a filter circuit. The first field-effect transistor supplies a bias signal to an amplifier. The filter circuit is connected between a collector terminal of the first bipolar transistor and the ground through a base terminal of the first bipolar transistor. The filter circuit has frequency characteristics for attenuating a high frequency component of an RF signal to be input to the amplifier.

Abstract: An apparatus includes a NMOS transistor having a drain, a first PMOS transistor having a drain connected to the drain of the NMOS transistor, a level shifter having an input and an output, the input of the level shifter being connected to the drain of the NMOS transistor and the drain of the first PMOS transistor, a first digital logic circuit having a drain and a gate, a first inverter having an input connected to the Aoutput of the level shifter and the drain of the first digital logic circuit, and a second digital logic circuit having an output connected to the gate of the first digital logic circuit, at least one condition being set in the apparatus during a read operation.

Abstract: A system and method for protecting against a voltage glitch are provided. Generally, the system includes a reset-detector coupled to a supply voltage (VCC) and to a power-on-reset (POR) block, and a glitch-detector coupled to VCC and the reset-detector. The reset-detector is operable to provide a signal to the POR block to generate a global-reset-signal when VCC decreases below a minimum and remains low for at least a first time. The glitch-detector is operable to provide a glitch-signal to the reset-detector to cause it to provide the signal to the POR block when VCC decreases below the minimum and remains low for at least a second time, where the second time is less than the first. The reset-detector can further include a retention-circuit operable to recall a glitch-signal was received and signal the POR block when VCC is restored. Other embodiments are also disclosed.

Abstract: Systems, methods, and apparatus for biasing a high speed and high voltage driver using only low voltage transistors are described. The apparatus and method are adapted to control biasing voltages to the low voltage transistors such as not to exceed operating voltages of the low voltage transistors while allowing for DC to high speed operation of the driver at high voltage. A stackable and modular architecture of the driver and biasing stages is provided which can grow with a higher voltage requirement of the driver. Capacitive voltage division is used for high speed bias voltage regulation during transient phases of the driver, and resistive voltage division is used to provide bias voltage at steady state. A simpler open-drain configuration is also presented which can be used in pull-up or pull-down modes.

Abstract: A switching device includes: a lower switching element, an upper switching element having a source connected to a drain of the lower switching element; a control circuit including a first output part that supplies a driving signal to the lower switching element; a Zener diode having a cathode connected to the first output part; a parallel capacitor connected to the Zener diode in parallel; a resistor connected between an anode of the Zener diode and a gate of the lower switching element; and a gate-side capacitor provided separate from a parasitic capacitance of the lower switching element, having a larger capacitance than the parasitic capacitance of the lower switching element, and connected, outside the lower switching element, between the gate and a source of the lower switching element. The capacitance of the gate-side capacitor is smaller than a capacitance of the parallel capacitor.

Abstract: A semiconductor device may include a bandgap circuit that outputs a reference voltage. The semiconductor device may also include a startup circuit coupled to the bandgap circuit. The startup circuit may connect a voltage source to a node that corresponds to an output of the bandgap circuit in response to the bandgap circuit being initialized. The startup circuit may also disconnect the voltage source from the node in response to the reference voltage being greater than a threshold.

Abstract: Provided is a power amplification circuit that includes: an amplifier that amplifies an input signal and outputs an amplified signal; a first bias circuit that supplies a first bias current or voltage to the amplifier; a second bias circuit that supplies a second bias current or voltage to the amplifier; a first control circuit that controls the first bias current or voltage; and a second control circuit that controls the second bias current or voltage. The current supplying capacity of the first bias circuit is different from the current supplying capacity of the second bias circuit.

Abstract: A memory system includes a connector through which power for the memory system is to be supplied from an external device, a controller, a nonvolatile memory device, a power source circuit connected to the controller and the nonvolatile memory device by power lines through which power is supplied to the controller and the nonvolatile memory device, and a power source control circuit that receives a supply of power from the external device through the connector and supplies the power to the power control circuit. The power source control circuit is configured to detect using a divided voltage of a voltage of the power supplied thereto, that the voltage of the power supplied thereto is higher than a predetermined voltage and interrupt the power supplied to the power control circuit if the voltage of the power supplied thereto is higher than the predetermined voltage.

Abstract: A power amplifier circuit includes a first transistor, a second transistor, a first bias circuit supplying a first bias current or voltage, a second bias circuit supplying a second bias current or voltage, a first inductor, and a first capacitor. A power supply voltage is supplied to a collector of the first transistor, and an emitter thereof is grounded. A radio frequency signal and the first bias current or voltage are supplied to a base of the first transistor. The power supply voltage is supplied to a collector of the second transistor, and an emitter thereof is connected to the collector of the first transistor via the first capacitor and is grounded via the first inductor. The second bias current or voltage is supplied to a base of the second transistor. An amplified radio frequency signal is output from the collector of the second transistor.

Abstract: A device (1) for delivering a signal switching from a first state to a second state, comprising: a primary circuit (4) generating a primary signal; and a secondary circuit (6) configured to: when the primary signal is initialized to the second state upon power-up, initialize a ring counter (16) to a random value in a finite sequence including a reference value, change the value of the first ring counter (16) by running through the first finite sequence in a circular fashion, and deliver at an output (3): i) a secondary signal in the first state, when the value of the first counter is different from the reference value, and ii) the primary signal, when the value of the first counter is equal to the reference value.

Abstract: Various implementations described herein may refer to level shifter circuitry using current mirrors. For instance, in one implementation, a level shifter circuit may include a latch circuit configured to receive an input signal, where the latch circuit includes a plurality of transistors configured to generate an output signal based on the input signal. The level shifter circuit may also include a first current mirror circuit coupled to the latch circuit. The level shifter circuit may further include a second current mirror circuit coupled to the latch circuit, where the first current mirror circuit and the second current mirror circuit are configured to drive the output signal from a transient state voltage level to a steady state voltage level.

Abstract: A semiconductor switch control circuit includes: a pulse signal generating part configured to generate a pulse signal which becomes a time reference for performing an ON/OFF control of a semiconductor switch; a drive current generating part configured to generate a drive current based on the pulse signal which the pulse signal generating part generates and to supply the drive current to a gate electrode of the semiconductor switch; a current detecting part configured to detect a drain current or a source current of the semiconductor switch; and a drive current control part configured to have a function of controlling a drive current which the drive current generating part generates based on the pulse signal which the pulse signal generating part generates and the current which the current detecting part detects.

Abstract: A power amplifier includes a distributor distributing an input first signal to a second signal and a third signal delayed by about 2? degrees (45<?<90) from the second signal, a first amplifier amplifying the second signal and outputting a fourth signal when a first-signal power level is not lower than a first level, a second amplifier amplifying the third signal and outputting a fifth signal when the first-signal power level is not lower than a second level that is greater than the first level, a first phase shifter receiving the fourth signal and outputting a sixth signal delayed by about ? degrees from the fourth signal, a second phase shifter receiving the fifth signal and outputting a seventh signal advanced by about ? degrees from the fifth signal, and a combiner combining the sixth and seventh signals and outputting an amplified signal of the first signal.

Abstract: A method for driving a load includes driving a load to an initial voltage within a voltage window, the voltage window based on an input voltage and an offset voltage, and driving the load to approximately the input voltage.