Abstract: A switching arrangement for switching off an electric current with a high slew rate, especially a short-circuit current, includes a main line with a first SCR-arrangement including at least a first SCR and a first reverse conducting diode arranged in parallel to the first SCR, and a first bypass line connected to the main line and arranged in a parallel way to the first SCR-arrangement. The first bypass line includes a second SCR-arrangement comprising at least a second SCR arranged in the same polarity as the first reverse conducting diode. The first bypass line further includes at least one capacitor and a DC-voltage source connected to the capacitor for pre-charging the capacitor.

Abstract: In described examples of a ramp circuit, a first terminal of a capacitor is coupled to a ramp terminal and a second capacitor terminal is coupled to a return terminal. A charge source has an input terminal coupled to a supply terminal and a charge output terminal. A resistor has a first terminal coupled to the return terminal. A first switch is coupled between the ramp terminal and a second terminal of the resistor. A second switch is coupled between the charge output terminal and the ramp terminal.

Abstract: Devices and methods include voltage buses. The devices also include one or more power amplifiers coupled to the voltage bus. Each of the one or more power amplifiers include one or more transistors. The devices also include a model that is configured to emulate leakage from at least one of the one or more transistors. A current mirror with a first transistor coupled to the model and a second transistor coupled to the voltage bus. The current mirror is configure to draw charge from the voltage bus based at least in part on the emulated leakage from the model.

Abstract: High-speed flipflop circuits are disclosed. The flipflop circuit may latch a data input signal or a scan input signal using a first signal, a second signal, a third signal, and a fourth signal generated inside the flipflop circuit, and may output an output signal and an inverted output signal. The flipflop circuit includes a first signal generation circuit configured to generate the first signal; a second signal generation circuit configured to generate the second signal; a third signal generation circuit configured to receive the second signal and generate the third signal; and an output circuit configured to receive the clock signal and the second signal, and output an output signal and an inverted output signal.

Abstract: A capacitive transmitter includes a control circuit configured to generate a data signal by delaying input data and to generate a control signal according to the input data and a delayed signal thereof; a capacitor connected between a first node and a transmission node; a driving circuit configured to receive the data signal and to provide an output signal corresponding to the data signal to the first node; and a bias setting circuit configured to set a transmission voltage at the transmission node according to the control signal.

Abstract: A down-conversion mixer includes a converting-and-mixing circuit and a load circuit. The converting-and-mixing circuit performs voltage to current conversion and mixing with a differential oscillatory voltage signal pair upon a differential input voltage signal pair to generate a differential mixed current signal pair. The load circuit includes two transistors each having a transconductance that varies according to a control voltage, two resistors each decreasing a threshold voltage of a respective one of the transistors, and a resistor-inductor circuit cooperating with the transistors to convert the differential mixed current signal pair into a differential mixed voltage signal pair.

Abstract: A flip-flop includes an input switching circuit configured to output an intermediate signal based on an input signal and at least one of a phase of a clock signal or a phase of an inverted clock signal, the phase of the inverted clock signal being opposite to the phase of the clock signal, and block application of a driving voltage to at least one circuit element of the input switching circuit in response to receiving a reset signal representing a reset operation of the flip-flop, and a latch circuit configured to generate an output signal based on the intermediate signal according to the at least one of the phase of the clock signal or the phase of the inverted clock signal.

Abstract: A bidirectional bipolar transistor switch arrangement, including: a first bipolar transistor and a second bipolar transistor connected in anti-parallel between a first terminal and a second terminal, a resistor connected to the base of the first bipolar transistor and the second bipolar transistor and to a control terminal, a first diode connected with anode to the first terminal, and a second diode connected with anode to the second terminal, the first diode and the second diode being connected via respective cathodes to a supply terminal. The bidirectional bipolar transistor switch arrangement is able to control the power supply within a daisy chain with low drop voltage.

Abstract: An electronic circuit, including a first switching device that contains a first semiconductor material with a first band gap, and a second switching device that is coupled in parallel to the first switching device, and contains a second semiconductor material with a second band gap smaller than the first band gap. Each of the first and second switching devices has a control electrode, and the control electrode of the first switching device is coupled to the control electrode of the second switching device.

Abstract: A counter is provided. A charge distributing circuit includes a first switch, a second switch, a third switch, a fourth switch, a third capacitor and a fourth capacitor. A first terminal of the first switch and a first terminal of the third switch are connected to a first input terminal of an operational amplifier. A second terminal of the first switch is connected to a first terminal of the third capacitor and a first terminal of the fourth switch. A second terminal of the third switch is connected to a first terminal of the fourth capacitor and a first terminal of the second switch. A second terminal of the third capacitor and a second terminal of the fourth capacitor are grounded. A second terminal of the second switch and a second terminal of the fourth switch are coupled to a reference voltage.

Abstract: A comparator configured to calibrate an offset according to a control signal, including an input circuit configured to receive a first input signal and a second input signal, and to generate a first internal signal corresponding to the first input signal and a second internal signal corresponding to the second input signal; a differential amplification circuit configured to consume a supply current flowing from a positive voltage node having a positive supply voltage to a negative voltage node having a negative supply voltage, and to generate an output signal by amplifying a difference between the first internal signal and the second internal signal; and a current valve configured to adjust at least a portion of the supply current based on the control signal.

Abstract: A voltage monitoring circuit monitors a magnitude relationship between a monitoring target voltage and a determination voltage and is capable of suppressing the influence of an offset of a reference voltage upon the determination voltage and setting the determination voltage as desired. The voltage monitoring circuit includes: an input terminal, applied with a monitoring target voltage or a divided voltage of the monitoring target voltage; a reference voltage generating circuit, generating a first reference voltage; a linear power circuit, converting the first reference voltage to a second reference voltage; a feedback resistor, generating a divided voltage of the second reference voltage, and negatively feeding back the divided voltage of the second reference voltage to the linear power circuit; and a comparing portion, comparing the second reference voltage with the monitoring target voltage or the divided voltage of the monitoring target voltage applied to the input terminal.

Abstract: An analog switch includes a first field effect transistor (FET) which has a first terminal coupled to an input voltage terminal, a second terminal coupled to a common source, and a control terminal coupled to a common gate. The switch includes a second FET which has a first terminal coupled to an output voltage terminal, a second terminal coupled to the common source, and a control terminal coupled to the common gate. The switch includes a switched current source which has an input coupled to a high voltage supply terminal and an output coupled to the common gate. The switch includes a clamp circuit which has a first terminal coupled to the common gate, a second terminal coupled to the common source, and a third terminal coupled to the low voltage supply terminal.

Abstract: A voltage comparator and an operation method thereof are provided. The voltage comparator includes an amplifying circuit, a reference current source, and a transient current source. A first input terminal and a second input terminal of the amplifying circuit respectively receive a first corresponding voltage corresponding to a target voltage and a reference voltage. The reference current source is coupled to the amplifying circuit to provide a reference current. The transient current source is coupled to the amplifying circuit to selectively provide a transient current. The transient current source detects a transition of a second corresponding voltage corresponding to the target voltage to dynamically adjust the transient current. Therefore, when a rapidly increasing voltage occurs in the target voltage, the transient current source may temporarily increase the current of the amplifying circuit, thereby accelerating the response speed of the amplifying circuit.

Abstract: In a method computer storage element operation, first and second rising (or falling) clock edges are applied to first and second power inputs of the computer storage element having a transistor array between the first and second power inputs over time T1 whereupon a logic value applied to an input of the transistor array is stored therein. Thereafter, first and second falling (or rising) clock edges are applied to the first and second power inputs over time T2, whereupon part of an electrical charge or energy associated with the logic value stored in the transistor array is provided to circuitry that generates the first and/or second clock edge(s), wherein the value(s) of time T1 and/or time T2 is/are greater than a product of RC, where R is resistance associated with the computer storage element, and C is a load capacitance associated with the computer storage element.

Abstract: An electronic device includes a driver that is connected with a pin, receives an input signal, and outputs an output signal to the pin in response to the input signal, a core circuit that transfers the input signal to the driver, and a monitor circuit that receives the input and output signals and detects a stuck voltage state of the output signal based on the input and output signals. The monitor circuit includes a first detection circuit that detects the stuck voltage state when the input and output signals are logically incorrect, a second detection circuit that detects the stuck voltage state when the input and output signals are logically correct and when the output signal is at a low level, and a third detection circuit that detects the stuck voltage state when the input and output signals are logically correct and when the output signal is at a high level.

Abstract: A level shift circuit includes an input section to which input signal of a first power supply system is input, a supply section that includes a pair of nodes, and a regulator. The supply section is connected to one of a pair of power supply lines serving as a second power supply system of which a voltage level is higher than a voltage level of the first power supply system, the supply section supplying a potential of the one of the pair of power supply lines to one of the pair of nodes according to the input signal. The regulator is connected to another of the pair of power supply lines, the regulator regulating current flowing between the one of the pair of nodes that is supplied with the potential of the one of the pair of power supply lines, and the other of the pair of power supply lines.

Abstract: A positive-logic FET switch stack that does not require a negative bias voltage, and which can withstand application of a high voltage RF signal without requiring terminal capacitors. Some embodiments include a stack of FET switches, with at least one FET requiring a negative VGS to turn OFF and configured so as to not require a negative voltage, series-coupled on at least one end to an end-cap FET that turns OFF when the VGS of such end-cap FET is essentially zero volts, wherein at least one end-cap FET is configured to be coupled to a corresponding RF signal source and has a gate coupled to the corresponding RF signal source through an associated switch circuit. The switch circuit may include an NMOSFET and a PMOSFET, or a diode and an NMOSFET, or a diode and an NMOSFET and a PMOSFET.

Abstract: A first current source and a third current source are coupled at a first output node. A second current source and a fourth current source are coupled at a second output node. Control terminals of a first transistor and a second transistor are coupled to the second output node. Control terminals of a third transistor and a fourth transistor are coupled to the first output node. The first transistor and a fifth transistor are coupled in series between a power terminal and the first output node. A sixth transistor and the second transistor are coupled in series between the first output node and a ground terminal. The third transistor and a seventh transistor are coupled in series between the power terminal and the second output node. An eighth transistor and the fourth transistor are coupled in series between the second output node and the ground terminal.

Abstract: A bus driving device includes at least three high-side output drivers and at least three low-side output drivers. A part of the high-side output drivers and a part of the low-side output drivers are alternately coupled in series, and the remains of the high-side output drivers and the low-side output drivers are alternately coupled in series. The part of the high-side output drivers and the part of the low-side output drivers receive an input digital signal and sequentially drive a first supply bus and a second supply bus based on the input digital signal, and the remains of the high-side output drivers and the low-side output drivers receive the inverted input digital signal and sequentially drive the first supply bus and the second supply bus based on the inverted input digital signal.