Abstract: The present disclosure discloses a source signal output circuit and an inverter thereof. The inverter is configured to provide a multiplexer with a control signal having a full range for selecting a source signal and to output the control signal having the full range by using elements operating in a low voltage range. Therefore, the present disclosure has an advantage in that it can fabricate a driving circuit having a small area at a low process cost.

Abstract: Apparatus and associated methods relate to a power supply noise disturbance rejection circuit (NDRC) having a first circuit reference potential (CRP1), a second circuit reference potential (CRP2), and a galvanic link conductively connecting CRP1 and CRP2 and providing a non-zero resistance return path for at least one current mode signal (CMS). In an illustrative example, a power supply monitor circuit (PSMC) may be referenced to CRP1 and a control circuit to CRP2. The PMSC may, for example, generate a voltage mode signal (VMS) relative to CRP1 and representing an output parameter of a power supply circuit (PSC), and convert the VMS into a first CMS (CMS1). The control circuit may, for example, generate a control signal for the PSC from CMS1. Various embodiments may advantageously attenuate a noise margin of a CMS presented at the control circuit by a factor of at least 10 relative to an equivalent VMS.

Abstract: Embodiments of the disclosure provide an input output (IO) structure in which complimentary nodes of a level shifter are utilized to logically block the output of the IO structure from switching until both power supplies to the IO structure are powered up. An illustrative level shifter includes: a cross-coupled pair of PFETs configured to output complimentary voltage values at a first node and a second node; a control circuit configured to select which of the complementary voltage values are output to the first node and second node; a logic inverter having an input coupled to the first node and an output coupled to a third node; and a NAND gate having inputs coupled to the second node and third node and that generates a level shifted output.

Abstract: An active mixer for frequency conversion used in a wireless communication system improves conversion gain and noise figure by improving switching characteristics of a mixer using a LO signal without requiring additional power consumption of an active mixer block. Further disclosed is a method for improving conversion gain and noise figure of an active mixer. The active mixer includes a switching stage for receiving a LO signal and selectively performing a switching-on/off operation for frequency conversion, a body signal generator for generating a body signal to be applied to a body of an NMOS transistor of the switching stage based on the LO signal, and a voltage controller for controlling the body signal generator to selectively apply the body signal to the body of the NMOS transistor based on to the switching-on/off operation of the switching stage to control a threshold voltage of the transistor of the switching stage.

Abstract: To provide a hysteresis comparator having a small circuit area and low power consumption. The hysteresis comparator includes a comparator, a switch, a first capacitor, a second capacitor, and a logic circuit. A first terminal of the switch is electrically connected to one of a pair of conductive regions of the first capacitor, one of a pair of conductive regions of the second capacitor, and a first input terminal of the comparator. An output terminal of the comparator is electrically connected to an input terminal of the logic circuit. An output terminal of the logic circuit is electrically connected to the other of the pair of conductive regions of the second capacitor. The logic circuit has a function of generating an inverted signal of a signal input to the input terminal of the logic circuit and outputting the inverted signal to the output terminal of the logic circuit. A reference potential is input to the first input terminal of the comparator and the reference potential is held by the switch.

Abstract: A control signal may be produced in response to an assertion of a switch signal by asserting the control signal, waiting an adaptive delay after the assertion of the switch signal, de-asserting the control signal in response to the expiration of the adaptive delay, and re-asserting the control signal in response to a current generated according to the control signal becoming zero. The adaptive delay may be adjusted according to a voltage generated using the current. A circuit may include an XOR gate producing the control signal from a switch signal and an output of a Set-Reset Flip-Flop (SRFF), a zero-detect circuit that resets the SRFF when a current generated using the control circuit becomes zero, and a delay circuit to set the SRFF an adaptive delay after assertion of the switch signal and to adjust the adaptive delay according to a voltage generated by the current.

Abstract: Systems and devices are provided for tracking pullup current generated by power amplifiers regardless of variations in PVT conditions. An apparatus may include one or more power amplifiers that powers components of the apparatus, a tracking circuit, and a pulse generation circuit. The tracking circuit may include an amplifier. Further, the tracking circuit may include pullup current tracking circuitry that is coupled to the amplifier and generates a first current that tracks pullup current generated by the one or more power amplifiers. Furthermore, the pulse generation circuit may include pullup current generator circuitry that generates a second current that mirrors the first current. In addition, the pulse generation circuit may also include pulse generator circuitry that is coupled to the pullup current generator circuitry and that generates a pulse to control operation of the one or more power amplifiers based at least in part on the second current.

Abstract: A circuit includes a peak detector, a diode, a dynamic clamp circuit, and an offset correction circuit. The peak detector generates a voltage on the peak detector output proportional to a lowest voltage on the peak defector input. The anode of the diode is coupled to the peak detector input. The dynamic clamp circuit is coupled to the peak detector input and is configured to clamp a voltage on the peak detector input responsive to a voltage on the diode's anode being greater than the lowest voltage on the peak detector's input. The offset correction circuit is coupled to the peak detector output and is configured to generate an output signal whose amplitude is offset from an amplitude of the peak detector output.

Abstract: A seat unit includes a light receiving circuit configured to output a pulsed light detection signal in two levels depending on a light reception, a switch input circuit configured to output a pulsed on-off signal in two levels depending on whether a switch mounted on the seat is turned on or turned off, a logic circuit configured to output a turn-on signal upon receipt of the light detection signal in a level indicating the light reception and the on-off signal in a turn-on level, a light emitting circuit configured to emit light upon receipt of the turn-on signal, and a delay circuit configured to delay the light detection signal. The switch input circuit cuts off, upon receipt of the delayed light detection signal in a level indicating no light reception, the power supply from a battery to the switch and to output the on-off signal in the turn-on level.

Abstract: An Integrated Circuit (IC) includes functional circuitry and attack-protection circuitry (APC). The functional circuitry is to receive a supply voltage from a power-supply input. The APC is coupled to the power-supply input and includes a front-end circuit and an averaging circuit. The front-end circuit is to compare the supply voltage to a plurality of voltage thresholds, and to output a respective plurality of indications that indicate whether the supply voltage violates the respective voltage thresholds. The averaging circuit is to estimate, for a selected subset of the indications, respective duty-cycles at which the indications in the subset exceed the respective voltage thresholds. The APC is to trigger one or more attack detection events in response to the indications and the duty-cycles.

Abstract: An embodiment device includes a first MOS transistor and a first resistor in series between first node and second nodes, the first resistor being connected to the second node; a second MOS transistor and a second resistor in series between the first and second nodes, the second resistor being connected to the second node and the gates of the first and second transistors being coupled to each other; an operational amplifier including a first terminal connected to a node of connection of the first resistor to the first transistor, a second terminal, and an output terminal coupled to the gate of the first transistor; and a circuit configured to supply a set point voltage to the second terminal of the amplifier.

Abstract: A load control device for controlling the amount of power delivered to an electrical load (e.g., an LED light source) includes first and second semiconductor switches, a transformer, a capacitor, a controller, and a current sense circuit operable to receive a sense voltage representative of a primary current conducted through a primary winding of the transformer. The primary winding is coupled in series with a semiconductor switch, while a secondary winding is adapted to be operatively coupled to the load. The capacitor is electrically coupled between the junction of the first and second semiconductor switches and the primary winding. The current sense circuit receives a sense voltage and averages the sense voltage when the first semiconductor switch is conductive, so as to generate a load current control signal that is representative of a real component of a load current conducted through the load.

Abstract: A logarithmic amplifier includes a logarithmic current preamplifier circuit and logarithmic amplifier circuit. The logarithmic current preamplifier circuit includes an inverting input terminal, an output terminal, and a first diode. The first diode is coupled between the inverting input terminal of the logarithmic current preamplifier circuit and the output terminal of the logarithmic current preamplifier circuit. The logarithmic amplifier circuit includes an inverting input terminal, an output terminal, and a second diode. The inverting input terminal of the logarithmic amplifier circuit is coupled to the output terminal of the logarithmic current preamplifier circuit. The second diode is coupled between the inverting input terminal of the logarithmic amplifier circuit and the output terminal of the logarithmic amplifier circuit.

Abstract: A clock circuit includes a latch circuit, a memory state latch circuit, a memory state trigger circuit and a clock trigger circuit. The latch circuit is configured to latch an enable signal, and to generate a latch output signal based on a first clock signal or an output clock signal. The memory state latch circuit is configured to generate the output clock signal responsive to a first control signal. The memory state trigger circuit is coupled to the memory state latch circuit, and configured to adjust the output clock signal responsive to the latch output signal. The clock trigger circuit is coupled to the latch circuit or the memory state trigger circuit by a first node, configured to generate the first clock signal responsive to a second clock signal, and configured to control the latch circuit and the memory state trigger circuit based on the first clock signal.

Abstract: A duty timing detector includes a saw-tooth voltage generator that outputs a saw-tooth voltage in synchronization with a toggle signal repeatedly transitioning between a high level and a low level. A sample block obtains a level of the saw-tooth voltage in synchronization with the toggle signal and outputs the obtained level as a first sample voltage. A hold block stores the first sample voltage in synchronization with the toggle signal and outputs the stored first sample voltage as a second sample voltage. A voltage divider divides the second sample voltage to output a division voltage. A comparator compares the saw-tooth voltage and the division voltage to detect a target timing in each duty of the toggle signal.

Abstract: A double-balanced mixer, including a coupling transformer, a first diode cascade circuit, a second diode cascade circuit, and a first set of coils, is provided. The coupling transformer receives a first input signal and generates at least one set of signals with opposite voltage phases. The first diode cascade circuit is coupled to the coupling transformer, and generates a first node voltage according to a first set of bias voltages. The second diode cascade circuit is coupled to the coupling transformer, and generates a second node voltage according to a second set of bias voltages. The first set of coils is coupled to the first and second diode cascade circuits, receives the first and second node voltages and a second input signal, and generates an output signal. The first node voltage is equal to the second node voltage.

Abstract: A mixer circuit including a mixer, a voltage divider circuit, and an amplifier, is provided. The mixer receives a first input signal, a second input signal, and at least one set of bias voltages, and generates an output signal. A frequency of the output signal is related to a frequency of the first input signal and a frequency of the second input signal. The voltage divider circuit receives the bias voltages and generates a common mode signal at an output end. The amplifier is coupled to the mixer to receive the output signal, and is coupled to the output end of the voltage divider circuit and configured to suppress noise in the output signal, and generate a final output signal.

Abstract: A frequency multiplier includes an input section to receive a quadrature phase input signal having an input frequency, a mixer section coupled to the input section by a common mode node that forms a path for the common mode signal current to flow to the mixer section and magnetically coupled to the common mode node or capacitively coupled to the input section to generate a differential switching voltage at odd multiples of twice the input frequency, which switching voltage is applied to inputs of the mixer section, and an output section magnetically coupled to the mixer section, the output section being configured to generate an output voltage having a dominate frequency and sub-dominate frequencies spaced apart by the first multiple, the dominate frequency of the output voltage being a second multiple of the input frequency, where the second multiple is greater than the first multiple. Various arrangements are provided.

Abstract: A power-on reset signal generating device includes a reference voltage generator, a signal driver, and a stabilization circuit. The reference voltage generator generates a power-on reference voltage based on a voltage level of a power supply voltage. The signal driver drives the power-on reference voltage to generate a power-on reset signal. The stabilization circuit receives the power-on reset signal to keep a voltage level of the power-on reference voltage staying during a predetermined amount of time.

Abstract: A feedback control circuit in an LED driving circuit for driving a plurality of LED strings. Each LED string provides a headroom detecting voltage. The feedback control circuit has a status detecting circuit, a counting circuit and a modulating circuit. The status detecting circuit compares each headroom detecting voltage with a low headroom threshold voltage and a high headroom threshold voltage and generates an up self-status signal and a down self-status signal. The counting circuit counts or keeps unchanged and then generates a counting signal based on the up self-status signal and the down self-status signal. The modulating circuit generates a modulating signal based on the counting signal. And based on the modulating signal, the feedback control circuit generates a feedback control signal to regulate a bias voltage supplying the plurality of LED strings.