Patents Examined by Mahmoud Dahimene
  • Patent number: 9453283
    Abstract: A method of manufacturing a nanowire includes: forming a silicon oxide layer by performing deposition of a silicon oxide on a substrate; forming a metal layer by performing deposition of a metal on the silicon oxide layer; forming a metal agglomerate by performing heat treatment on the substrate where the metal layer is formed; and growing a nanowire in an area where the metal agglomerate is formed by performing plasma treatment on the substrate where the metal agglomerate is formed.
    Type: Grant
    Filed: February 17, 2015
    Date of Patent: September 27, 2016
    Assignee: Samsung Display Co., Ltd.
    Inventor: Kyung Min Choi
  • Patent number: 9434879
    Abstract: Liquid compositions for etching glass are disclosed herein. The liquid composition may include a non-active etching agent precursor that is inactive with respect to chemically etching glass in an amount of at least 2.5% by weight of the total composition, a binder and a liquid vehicle. The precursor may include an alkali metal salt having an activation temperature of at least 400° C. and when heated to above the activation temperature, the precursor yields an active etching agent suitable for chemical etching of glass.
    Type: Grant
    Filed: November 25, 2014
    Date of Patent: September 6, 2016
    Assignee: DIP TECH LTD.
    Inventors: Matti Ben-Moshe, Michael Kheyfets
  • Patent number: 9431262
    Abstract: The method of the present invention is capable of polishing a high hardness work at high polishing efficiency. The method comprises the steps of: pressing a surface of the work onto a polishing part of a rotating polishing plate; and supplying slurry while performing the pressing step. The method is characterized in that an activated gas, which has been activated by gas discharge, is turned into bubbles and mixed into the slurry.
    Type: Grant
    Filed: March 4, 2015
    Date of Patent: August 30, 2016
    Assignee: FUJIKOSHI MACHINERY CORP.
    Inventors: Kazutaka Shibuya, Yoshio Nakamura
  • Patent number: 9412405
    Abstract: According to one embodiment, disclosed is a pattern forming method including preparing a second dispersion by adding a second protective group and second solvent to fine particles including a first protective group whose surface polarity is close to that of the substrate, the fine particles containing, at least on the surface thereof, a material selected from Al, Ti, V, Cr, Mn, Fe, Co, Ni, Zn, Y, Zr, Sn, Mo, Ta, W, Au, Ag, Pd, Cu, Pt, and an oxide thereof, modifying the fine particles including the first protective group with the second protective group, adding a viscosity adjustment agent to the dispersion containing the fine particles to prepare a coating solution, and applying the coating solution on the substrate to form a fine particle layer thereon.
    Type: Grant
    Filed: August 8, 2014
    Date of Patent: August 9, 2016
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Kaori Kimura, Akira Fujimoto, Akira Watanabe
  • Patent number: 9412567
    Abstract: A plasma monitoring method using a sensor, the sensor having a substrate; a first electrode, the first electrode being a conductive electrode and formed on the substrate while being isolated from the substrate; an insulating film formed on the first electrode; a contact hole formed in the insulating film and having a depth from a surface of the insulating film to the first electrode; and a second electrode, the second electrode being a conductive electrode, formed on the surface of the insulating film, and faced to plasma during a plasma process, the plasma monitoring method including measuring and monitoring potentials of the first electrode and the second electrode or a potential difference between the first electrode and the second electrode during the plasma process is disclosed. A plasma monitoring system carrying out the plasma monitoring method is also disclosed.
    Type: Grant
    Filed: March 4, 2015
    Date of Patent: August 9, 2016
    Assignees: LAPIS SEMICONDUCTOR CO., LTD., TOHOKU UNIVERSITY
    Inventors: Tomohiko Tatsumi, Seiji Samukawa
  • Patent number: 9390893
    Abstract: A method for achieving sub-pulsing during a state is described. The method includes receiving a clock signal from a clock source, the clock signal having two states and generating a pulsed signal from the clock signal. The pulsed signal has sub-states within one of the states. The sub-states alternate with respect to each other at a frequency greater than a frequency of the states. The method includes providing the pulsed signal to control power of a radio frequency (RF) signal that is generated by an RF generator. The power is controlled to be synchronous with the pulsed signal.
    Type: Grant
    Filed: August 22, 2014
    Date of Patent: July 12, 2016
    Assignee: Lam Research Corporation
    Inventors: John C. Valcore, Jr., Harmeet Singh, Bradford J. Lyndaker
  • Patent number: 9384999
    Abstract: A plasma etching method that can prevent residues from becoming attached to bottoms and sides of via holes and trenches. An interlayer insulation film formed of CwFx (x and w are predetermined natural numbers) and a metallic layer or a metal-containing layer formed on a substrate are exposed at the same time to plasma generated from a process gas. The process gas is a mixed gas including CyFz (y and z are predetermined natural numbers) gas and N2 gas, and the flow rate of the N2 gas in the process gas is higher than the flow rate of the CyFz gas.
    Type: Grant
    Filed: October 21, 2008
    Date of Patent: July 5, 2016
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Naotsugu Hoshi, Noriyuki Kobayashi
  • Patent number: 9378966
    Abstract: A method of preparing an etch solution and thinning semiconductor wafers using the etch solution is proposed. The method includes steps of creating a mixture of hydrofluoric acid, nitric acid, and acetic acid in a solution container in an approximate 1:3:5 ratio; causing the mixture to react with portions of one or more silicon wafers, the portions of the one or more silicon wafers are doped with boron in a level no less than 1×1019 atoms/cm3; collecting the mixture after reacting with the boron doped portions of the one or more silicon wafers; and adding collected mixture back into the solution container to create the etch solution.
    Type: Grant
    Filed: June 10, 2014
    Date of Patent: June 28, 2016
    Assignee: International Business Machines Corporation
    Inventors: Brown C. Peethala, Spyridon Skordas, Da Song, Allan Upham, Kevin R. Winstel
  • Patent number: 9368365
    Abstract: A manufacturing method for forming a semiconductor structure includes: first, a plurality of fin structures are formed on a substrate and arranged along a first direction, next, a first fin cut process is performed, so as to remove parts of the fin structures which are disposed within at least one first fin cut region, and a second fin cut process is then performed, so as to remove parts of the fin structures which are disposed within at least one second fin cut region, where the second fin cut region is disposed along at least one edge of the first fin cut region.
    Type: Grant
    Filed: May 12, 2015
    Date of Patent: June 14, 2016
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Shih-Hsun Kuo, Ting-Cheng Tseng, Tan-Ya Yin, Chia-Wei Huang, Ming-Jui Chen
  • Patent number: 9368350
    Abstract: A method for DSA fin patterning includes forming a BCP layer over a lithographic stack, the BCP layer having first and second blocks, the lithographic stack disposed over a hard mask and substrate, and the hard mask including first and second dielectric layers; removing the first block to define a fin pattern in the BCP layer with the second block; etching the fin pattern into the first dielectric layer; filling the fin pattern with a tone inversion material; etching back the tone inversion material that overfills the fin pattern; removing the first dielectric layer selectively to define an inverted fin pattern from the tone inversion material; etching the inverted fin pattern into the second dielectric layer of the hard mask; removing the tone inversion material; and transferring the inverted fin pattern of the second dielectric layer into the substrate to define fins.
    Type: Grant
    Filed: June 23, 2015
    Date of Patent: June 14, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Hong He, Chi-Chun Liu, Alexander Reznicek, Chiahsun Tseng, Tenko Yamashita
  • Patent number: 9362149
    Abstract: Provided is a method of etching a silicon oxide film, which includes supplying a mixture gas of a halogen element-containing gas and a basicity gas onto a surface of the silicon oxide film; modifying the silicon oxide film to produce a reaction product; and heating the reaction product to remove the reaction product. Modifying the silicon oxide film and heating the reaction product are performed using one chamber. In heating the reaction product, the reaction product is selectively heated by a heating unit.
    Type: Grant
    Filed: September 8, 2014
    Date of Patent: June 7, 2016
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Yusuke Muraki, Shigeru Kasai, Tomohiro Suzuki
  • Patent number: 9358093
    Abstract: The present disclosure relates to a bioimplantable device having a superhydrophobic surface and a method for manufacturing the same. The bioimplantable device, which includes a biocompatible substrate and a superhydrophobic nanostructure formed on the surface of the biocompatible substrate, is capable of preventing blood clot formation by blocking contact with proteins, water, blood platelets, etc. when used for blood vessels.
    Type: Grant
    Filed: December 13, 2012
    Date of Patent: June 7, 2016
    Assignee: KOREA INSTITUTE OF SCIENCE AND TECHNOLOGY
    Inventors: Soo Hyun Kim, Jin Ik Lim, Youngmee Jung
  • Patent number: 9340411
    Abstract: Techniques herein enable executing directed self-assembly of block copolymer patterning processes that result in patterns having no defects or a negligibly low occurrence of defects to have a high yield of functional patterns and devices. Methods include executing a same DSA patterning sequence two or more times such that any defects in from a phase-separated first block copolymer film are corrected with a phase-separated second block copolymer film as any defect in the second block copolymer film would only temporarily cover a feature already created and/or transferred from first block copolymer film.
    Type: Grant
    Filed: January 23, 2015
    Date of Patent: May 17, 2016
    Assignee: Tokyo Electron Limited
    Inventor: Anton J. deVilliers
  • Patent number: 9330888
    Abstract: The present invention discloses a dry etching method. The dry etching method comprises: etching a first medium layer; introducing a second reaction gas in a reaction chamber, and exciting the second reaction gas into plasmas with a second radiofrequency power, so that the plasmas formed from the second reaction gas are combined with particulate pollutants in the reaction chamber, and in this case the reaction chamber is vacuumized to perform conversion processing; and etching a second medium layer. The technical solution of the present invention is capable of effectively preventing particulate pollutants from falling onto the glass substrate in the procedure of executing conversion processing, meanwhile, the effect of chamber purifying through vacuumizing is improved, and the amount of the particulate pollutants in the reaction chamber is effectively reduced.
    Type: Grant
    Filed: July 31, 2014
    Date of Patent: May 3, 2016
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., BEIJING BOE DISPLAY TECHNOLOGY CO., LTD.
    Inventors: Xiangqian Ding, Yao Liu, Xi Chen, Liangliang Li, Jinchao Bai, Xiaowei Liu
  • Patent number: 9324569
    Abstract: A groove shape can be improved. A plasma etching method includes plasma-processing a photoresist film that is formed on a mask film and has a preset pattern; exposing an organic film formed under the mask film by etching the mask film with the pattern of the plasma-processed photoresist film; and etching the organic film by plasma of a mixture gas containing O2 (oxygen), COS (carbonyl sulfate) and Cl2 (chlorine).
    Type: Grant
    Filed: June 26, 2014
    Date of Patent: April 26, 2016
    Assignee: TOKYO ELECTRON LIMITED
    Inventor: Takayuki Ishii
  • Patent number: 9318340
    Abstract: A method of manufacturing a semiconductor device including a wafer using a plasma etching device which includes a chamber, a chuck provided in the chamber to dispose a wafer to be processed thereon, a focus ring disposed at a peripheral edge portion of the chuck, and a gas supplying mechanism configured to supply various types of gases depending a radial position of the wafer. The method includes: placing a wafer formed with an organic film on the chuck; introducing an etching gas which etches the organic film on the wafer from the process gas supplying mechanism to a central portion of the wafer; introducing an etching inhibiting factor gas having a property of reacting with the etching gas to the peripheral edge portion of the wafer from the gas supplying mechanism; and performing plasma etching on the wafer using the etching gas.
    Type: Grant
    Filed: October 25, 2012
    Date of Patent: April 19, 2016
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Takayuki Katsunuma, Masanobu Honda, Kazuhiro Kubota, Hironobu Ichikawa
  • Patent number: 9312142
    Abstract: Methods for polishing a semiconductor wafer using a pad resurfacing arm and an apparatus therefor are disclosed. Embodiments may include providing a semiconductor wafer on a chemical mechanical polishing (CMP) tool, the CMP tool including a polish pad and a pad resurfacing arm which includes a pad cleaning part, a pad conditioning part, and a slurry dispensing part, dispensing a slurry to the polish pad utilizing the pad resurfacing arm, and polishing the semiconductor wafer utilizing the polish pad.
    Type: Grant
    Filed: June 10, 2014
    Date of Patent: April 12, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventor: Jens Kramer
  • Patent number: 9305583
    Abstract: A method provides a magnetic transducer having an air-bearing surface (ABS) location. An intermediate layer that includes a first sublayer in a side shield region and a second sublayer outside of the side shield region is provided. A trench is formed in the intermediate layer using multiple etches. A first etch removes part of the second sublayer, providing a first portion of the trench having a first sidewall angle. A second etch removes part of the first sublayer, providing a second portion of the trench having a second sidewall angle. The second sidewall angle is greater than the first sidewall angle. A main pole is provided in the trench and has a plurality of sidewalls. The sidewalls have the second sidewall angle in the second portion of the trench and at least one main pole sidewall angle corresponding to the first sidewall angle in the first portion of the trench.
    Type: Grant
    Filed: May 16, 2014
    Date of Patent: April 5, 2016
    Assignee: Western Digital (Fremont), LLC
    Inventors: Jinqiu Zhang, Feng Liu, Hongmei Han, Ming Sun, Xiaotian Zhou
  • Patent number: 9304255
    Abstract: An optical device includes an SOI substrate, the embedded insulating layer having a thickness of 200 nanometers (nm) or less; an optical waveguide comprising a Group III-V compound semiconductor material formed on top of the SOI substrate; and an optical leakage preventing layer formed inside the SOI substrate on a bottom side of the optical waveguide to prevent leakage of light from inside the optical waveguide towards the SOI substrate.
    Type: Grant
    Filed: June 24, 2015
    Date of Patent: April 5, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Shigeru Nakagawa, Seiji Takeda
  • Patent number: 9296205
    Abstract: Provided are a large-area nano-scale active printing device, a fabricating method of the same, and a printing method using the same. The printing device may include a substrate, first interconnection lines extending along a first direction, on the substrate, an interlayered dielectric layer provided on the first interconnection lines to have holes partially exposing the first interconnection lines, second interconnection lines provided adjacent to the holes in the interlayered dielectric layer to cross the first interconnection lines, and wedge-shaped electrodes provided at intersections with the first and second interconnection lines and connected to the first interconnection lines. The wedge-shaped electrodes protrude upward at centers of the holes.
    Type: Grant
    Filed: June 12, 2015
    Date of Patent: March 29, 2016
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Yong Suk Yang, In-Kyu You, Soon-Won Jung, Bock Soon Na, Seok-Hwan Moon