Abstract: A three-terminal device constructed from a Josephson junction with one or more asymmetric control lines is disclosed. The device is constructed with high temperature superconducting materials. The junction can be a bicrystal, SNS (Superconducting-Normal-Superconducting) or any other type of high temperature superconductor junction. The control line is either a conducting or superconducting material which is electrically isolated from the junction but inductively coupled into the junction. A portion of the control line is approximately directly above the junction and has current which at least partially flows parallel or nonparallel to current flowing across the junction. The control line current alters the magnetic field within the junction which changes the critical current of the junction. The junction is in a superconducting or resistive state depending on whether the bias current of the junction is greater than or less than the control current.

Abstract: A vertical transistor is provided on and extends in a first direction along a surface of a substrate. A bump electrode is formed over the transistor and crosses the transistor in a second direction perpendicular to the first direction. The bump electrode is butterfly-shaped and has a first area overlapping the transistor and a second area that does not overlap with the transistor. The size of the second area in the first direction is greater than the size of the first area in the first direction. The bump electrode shape has no interior angle exceeding 270.degree..

Abstract: A structure for improving latch-up immunity and interwell isolation in a semiconductor device is provided. In one embodiment, a substrate has an upper surface and a first dopant region formed therein. The first dopant region has a lower boundary located below an upper surface of the substrate and a side boundary extending from the upper surface of the substrate to the lower boundary of the first dopant region. A heavily doped region having a first portion and a second portion located along the lower boundary and the side boundary of the first dopant region, respectively, has a substantially uniform dopant concentration greater than a dopant concentration of the first dopant region. The heavily doped region improves latch-up immunity and interwell isolation without degrading threshold voltage tolerance.

Abstract: A buried bit line cell and a manufacturing method thereof increases the integration density of a semiconductor device such as a DRAM.

Abstract: The invention provides two kinds of structures for a thin-film solar cell that is improved in the adhesive strength and reflectance of a back surface electrode layer. According to the first structure, in a thin-film solar cell in which a transparent electrode layer, a thin-film semiconductor layer, and a back surface electrode layer are laid in stated order on an insulative transparent substrate, the back surface electrode layer consists of a first transparent conductive metal compound layer having a smaller refractive index than a semiconductor that constitutes the thin-film semiconductor layer, a second transparent conductive metal compound layer, and a metal layer. The second transparent conductive metal compound layer contains at least one of components of the first transparent conductive metal compound layer and a component of the metal layer.

Abstract: An (E)EPROM is provided in which information is written with hot electrons generated in the channel current at the source side of the channel instead of at the drain side, as is usual. To obtain the electric field distribution in the channel 6 necessary for this, the gate oxide 10 is provided with a thickened portion 13 adjacent the source zone 4 so that locally a strong lateral electric field is induced in the channel at higher gate voltages. An efficient charge transport of electrons to the floating gate 9 is obtained through this lateral electric field in the channel and the comparatively high electric field in the gate oxide. The thickened portion of the gate oxide may be obtained in a simple manner through thermal oxidation. To prevent the formation of strong fields at the drain side of the channel, the drain is preferably provided with an LDD structure 5a which adjoins the gate oxide. As a result, Fowler-Nordheim tunnelling through this thin gate oxide may also be used for erasing.

Abstract: A method is provided for forming a landing pad of a semiconductor integrated circuit, and an integrated circuit formed according to the same. A plurality of conductive regions are formed over a substrate. A polysilicon landing pad is formed over at least one of the plurality of conductive regions. After the polysilicon is patterned and etched to form the landing pad, tungsten is then selectively deposited over the polysilicon to form a composite polysilicon/tungsten landing pad which is a good etch stop, a good barrier to aluminum/silicon interdiffusion and a good conductor.

Abstract: An integrated circuit package of this invention includes a series of nonconductive rigid substrates, each substrate having a pattern of generally coplanar bond fingers embedded thereupon. An integrated circuit die is connected to individual bond fingers of varying bond finger patterns. Individual bond fingers are connected to package terminals by medial leads, which are generally perpendicular to the bond finger patterns. Semiconductor die packages having both top and bottom package terminals are thus produced. Methods and devices are shown.

Abstract: The invention relates to a device structure and crystal growth process for making the same, whereby single-crystal semiconductor layers are formed over metal or composite layers. The metal layers function as buried reflectors to enhance the performance of LEDs, solar cells, and photodiodes. The structure may also have application to laser diodes. The structures are made by a modification of a well-established metallic solution growth process. The lateral overgrowth process can be enhanced by imposing an electric current at the growth interface (termed liquid-phase electro-epitaxy). However, the use of an electric current is not crucial. The epitaxial lateral overgrowth technique was also applied to silicon growth on metal-masked silicon substrates.

Abstract: An attachment system (10,30) for electronic devices utilizes an interconnect substrate (11) and an attachment area (12,32) formed thereon. A non-wettable material (16,36) on a surface (13) of the substrate (11) substantially prevents an attachment material (17) from forming stress or cracks in the substrate (11).

Abstract: A resistor structure suitable for use in an SRAM cell is formed from polycrystalline silicon elements. These elements have a cross-section which is less than is normally available for polycrystalline silicon interconnect lines, allowing increased resistance values to be implemented using a lesser amount of surface area. In one embodiment of a resistor, sidewall spacers are formed in a cavity within an insulating layer, and polycrystalline silicon resistive elements are formed in the narrowed region within the cavity. In another embodiment, polycrystalline silicon resistors alongside vertical sidewalls of a cavity are formed using sidewall spacer technology. In either event, the cross-sectional area of the resistors is less than that normally available for a given processing technology, resulting in enhanced resistor values.

Abstract: A connection hole of a semiconductor device having a structure of preventing the connection hole from being short-circuited or degraded in dielectric strength even if there occurs misalignment when an opening portion is formed in an interlayer insulating film at a position over a conductive layer for forming the opening portion. The connection hole includes an inner wall on which an insulating film protected by a side wall made from non-crystal silicon is formed.

Abstract: A semiconductor device and a method for forming the same are disclosed. The semiconductor device comprising an insulated gate field effect transistor provided with a region having added thereto an element at least one selected from the group consisting of carbon, nitrogen, and oxygen, said region having established at either or both of the vicinity of the boundary between the drain and the semiconductor layer under the gate electrode and the vicinity of the boundary between the source and the semiconductor layer under the gate electrode for example by ion implantation using a mask. It is free from the problems of reverse leakage between the source and the drain, and of throw leakage which occurs even at a voltage below the threshold ascribed to the low voltage resistance between the source and the drain.

Abstract: A Josephson junction includes a substrate, a first superconducting layer, a second superconducting layer transversely overlaid on the first layer with an insulating layer interposed therebetween, the insulating layer is an oxide or a nitride of the superconducting material, and the insulating layer including a low oxygen- or nitrogen-concentrated area in contact with each of the first and second layers. A process for fabricating the Josephson junction includes the steps of preparing a substrate, forming a first superconducting layer, forming a second superconducting layer transversely on the first layer with an insulating layer interposed therebetween wherein the insulating layer is an oxide or nitride of the superconducting material, and injecting ion beams into the insulating layer so as to form low oxygen- or nitrogen-concentrated area linking the first and second layers.

Abstract: A semiconductor device includes a first semiconductor layer formed of first semiconductor, a second semiconductor layer formed on the first semiconductor layer and formed of second semiconductor of a group different from a group to which the first semiconductor belongs, and a third semiconductor layer formed between the first and second semiconductor layers, the third semiconductor layer being one of a layer formed of third semiconductor of the same group as the first semiconductor and having an impurity concentration higher than the first semiconductor layer and a layer formed of fourth semiconductor of the same group as the second semiconductor and having an impurity concentration higher than the second semiconductor layer.

Abstract: As the semiconductor chip is large-sized, highly integrated and speeded up, it becomes difficult to pack the semiconductor chip together with leads in a package. In view of this difficulty, there has been adopted the package structure called the "Lead-On-Chip" or "Chip-On-Lead" structure in which the semiconductor and the leads are stacked and packed. In the package of this structure, according to the present invention, the gap between the leading end portions of the inner leads and the semiconductor chip is made wider than that between the inner lead portions except the leading end portions and the semiconductor chip thereby to reduce the stray capacity, to improve the signal transmission rate and to reduce the electrical noises.

Abstract: A semiconductor chip package includes a substrate having a first surface and a second surface and a gap extending from the first surface to the second surface. The substrate defines a plane which is substantially parallel to the first and second surfaces. The substrate has conductive terminals accessible and the second surface and bond pads. Conductive leads extend across the gap whereby each lead electrically interconnects one of the conductive terminals and one of the bond pads. Each lead includes an expansion section within the gap which is laterally curved with respect to the plane. A semiconductor chip having a back surface and a face surface is assembled to the substrate. The face surface includes a plurality of contacts on the periphery of the face surface of the chip whereby the chip contracts are electrically connected to the bond pads on the substrate.

Abstract: By employing the structure that in a two-layer lead frame comprising a lamination layer of lead portions and a metal layer, the thickness of an adhesive layer for fixing the a semiconductor element to the adhesive layer is defined to be from 100 to 350 .mu.m and the semiconductor element is buried in the adhesive layer in a depth of at least 1/3o the thickness of the semiconductor element, the extent of the unevenness in the resin-sealed region is reduced and the occurrences of die shift and void are restrained.

Abstract: Increased gain and improved stability are realized in using resistive emitter ballasting by including integrated capacitive elements in parallel with the resistive elements in the emitter circuit. A feature of the invention is an integrated capacitor structure having a small surface area to minimize parasitic capacitance, whereby resistor and capacitor surface areas of 100 square micrometers or less are obtained. Another feature of the invention is the use of a high dielectric material in realizing a resistor-capacitor impedance zero at a frequency much lower than the operating frequency of the transistor. For an operating frequency of 2 GHz and resistor values of 50-250 ohms, capacitance required is 3 pF or greater. Another feature of the invention is a method of fabricating the integrated resistive-capacitive element in either a low temperature process or a high temperature process which minimizes capacitor leakage when using a thin high dielectric insulative material between capacitor plates.

Abstract: A semiconductor device which comprises a first lead having a tip formed with an island, a semiconductor chip unit mounted on the island of the first lead by means of a solder layer and having a plurality of electrode bumps projecting away from the island, and a plurality of additional leads each of which has a tip electrically connected to the electrode bumps via respective solder deposits. The additional leads include at least second and third leads. The tips of the second and third leads are at least partially wider than the semiconductor chip.