Surface field effect transistor with depressed source and/or drain areas for ULSI integrated devices

Abstract

A surface field effect integrated transistor has the surface of the silicon in the source and drain areas lowered by 50-500 nm in respect to the surface of the silicon underneath the gate electrode by etching the silicon substrate before forming the source and drain junctions.The transistor is sturdy and reliable because of the backing-off of the multiplication zone of the charge carriers from the gate oxide by a distance greater than several times the mean free path of hot carriers, thus markedly reducing the number of hot carriers available for injection in the gate oxide.The modified fabrication steps are readily integrable in a normal CMOS fabrication process.

Claims

5. The transistor according to claim 4, wherein said drain and source regions.Iadd.each.Iaddend.comprise a first region having a concentration of dopant atoms markedly lower than the concentration of dopant atoms of a second inner region contained within said first region.

6. The transistor of claim 1 wherein said drain region is rounded at its bottom corner..Iadd.7. The transistor of claim 1, wherein said source and drain regions are mutually symmetrical..Iaddend..Iadd.8. The transistor of claim 1, wherein said source and drain regions each comprise two different dopant species with different diffusivities..Iaddend..Iadd.9. An integrated circuit insulated gate field effect transistor structure, comprising:

a body of semiconductor material;

source and drain diffusions of a first conductivity type at said first surface of said body, said source and drain regions defining a channel region of a second conductivity type therebetween, said second conductivity type being different from said first conductivity type:

a gate structure overlying said first surface above said channel region, and capacitively coupled to said channel region through a thin gate oxide layer;

wherein said first surface of said body is recessed over said drain region, to a depth of between 50 and 500 nanometers below the level of said first surface under said gate structure;

and wherein said drain comprises two different dopant species of the same

type having different diffusivities..Iaddend..Iadd.10. The transistor of claim 9, wherein said source and drain regions are mutually symmetrical..Iaddend..Iadd.11. The structure of claim 9, wherein said common conductivity type is N-type..Iaddend..Iadd.12. The structure of claim 9, wherein said semiconductor material comprises silicon, and said source and drain regions each comprise silicide cladding at a respective surface thereof..Iaddend..Iadd.13. The structure of claim 9, wherein said first surface is radiused near the boundary between said drain region and said channel region..Iaddend..Iadd.14. The structure of claim 9, wherein said gate structure comprises polycrystalline silicon..Iaddend..Iadd.15. The structure of claim 9, wherein said gate structure comprises polycrystalline silicon overlaid with silicide cladding at a surface thereof..Iaddend..Iadd.16. An integrated circuit insulated gate field effect transistor structure, comprising:

a body of semiconductor material;

source and drain diffusions of a first conductivity type at said first surface of said body, said source and drain regions defining a channel region of a second conductivity type therebetween, said second conductivity type being different from said first conductivity type;

a gate structure overlying said first surface above said channel region, and capacitively coupled to said channel region through a thin gate oxide layer; said gate structure comprising a dielectric sidewall spacer on the sidewall of said gate structure adjacent to said drain diffusion;

wherein said first surface of said body is recessed over said drain region, to a depth of between 50 and 500 nanometers below the level of said first surface under said gate structure, and wherein said spacer extends down below the rest of said gate structure, to said first surface over said drain diffusion;

wherein said drain has a graded diffusion boundary, corresponding to multiple diffusions with dopants of said second type, adjacent said channel..Iaddend..Iadd.17. The structure of claim 16, wherein said common conductivity type is N-type..Iaddend..Iadd.18. The surface of claim 16, wherein said source and drain regions each comprise two different dopant species with different diffusivities..Iaddend..Iadd.19. The structure of claim 16, wherein said semiconductor material comprises silicon, and said source and drain regions each comprise silicide cladding at a respective surface thereof..Iaddend..Iadd.20. The structure of claim 16, wherein said first surface is radiused near the boundary between said drain region and said channel region..Iaddend..Iadd.21. The structure of claim 16, wherein said gate structure comprises polycrystalline silicon..Iaddend..Iadd.22. The structure of claim 16, wherein said gate structure comprises polycrystalline silicon overlaid with silicide cladding at a surface thereof..Iaddend.