Abstract: The invention is directed to a BGA package and method for making a BGA package in which warpage, delamination and package cracking are reduced. The inventive BGA package has a die attached to one surface of a substrate. The substrate may terminate at its opposite surface in an array of connection ports which is an integral part of the substrate. Alternatively, the array of connection ports is attached to the opposite surface of the substrate. The connection ports may be attach pads attached to the opposite surface of the substrate and solder balls or metal bumps attached to the attach pads. A matrix of molding compound fully encapsulates the substrate, die and the array of connection ports. The matrix molding compound is then ground to provide a flat surface and to expose portions of the connection ports. Another array of connection ports, such as an array of solder balls or metal bumps, may be attached to the existing array of connection ports.

Abstract: A platform carries an integrated circuit (IC) (20) for handling and alignment through wire bonding or TAB operations, provides interconnections, and supports the shielded IC with uniform, controlled adhesive thickness. The platform base (10) has a flat portion which may have a slot (30) extending the length of a chip with wire-bond pads (140). The IC is mounted to the platform base with cast or contained adhesive, epoxy, or tape (50), which provides at least one adhesive surface. For several rows of wire-bond pads, there may be several slots. If the platform carries more than one chip, the platform base may have one or more slots (30, 40) per chip. A platform may carry other components (110, 120). Circuitry (90) may be printed on one or both sides of the platform base, with moderate resistivity to damp ringing of noise signals. Wire bonds are made through the slot (30), connecting IC pads with circuitry.

Abstract: A semiconductor device comprises a semiconductor acceleration sensor having a cuboid-shaped cantilever cut from a semiconductor wafer, a detecting device disposed on the cantilever for detecting a displacement of the cantilever due to an acceleration force applied to the cantilever, and a supporter for supporting and fixing the cantilever at one end thereof.

Abstract: A package for an integrated circuit that contains a plurality of small circular dielectric spaces which separate vias from a conductive plane of the package. The package has a first internal conductive plane, a second internal conductive plane and a plurality of bond pads located on a top surface of a substrate. The substrate has a plurality of vias that extend through the first conductive plane to couple the second conductive plane to the bond pads. The package has a plurality of concentric dielectric clearance spaces that separate the vias from the first conductive plane. The small concentric spaces optimize the area of the conductive plane to minimize the resistance and maximize the capacitance of the package.

Abstract: A method and apparatus for inspecting wirings of an electronic circuit substrate to detect a defect in the wiring and for enabling correction thereof. The inspection method and apparatus include electrostatically coupling at least one electrode to a wiring pattern, applying a time varying voltage between the electrode and wiring pattern at different locations so as to detect a current flow and determine a defect by a variation in the detected current flow at the different locations and a portion of the defect. A defect in the form of a disconnected or half-disconnected point of the wiring may be corrected by supplying a solution of a metal complex to the disconnected or half-disconnected point, heating the solution and end point areas of the disconnected or half-disconnected point by laser light and precipitating a metal thin film establishing a connection of the wiring.

Abstract: A semiconductor chip is mounted on a die pad of a lead-frame, and the semiconductor chip mounted on the die pad is sealed in a plastic package; a side surface of the semiconductor chip and an exposed upper surface and a side surface of the die pad are covered with an organic stress relaxation layer so as to reduce a thermal stress due to the difference in thermal expansion coefficient between the semiconductor chip and the die pad, thereby presenting the plastic package from a crack.

Abstract: A chip cover for complete or partial covering of electrical, electronic, optoelectronic and/or electromechanical components includes an activator capable of fully or partially destroying the electrical, electronic, optoelectronic and/or electromechanical components of the chip when activated. The activator can be activated by an attempt to remove the chip cover from the chip. In this way it is possible to reliably prevent reverse engineering and/or manipulation of the chip.

Abstract: A device with power semiconductor components includes, in combination: a stack alternately comprising at least one power semiconductor component and at least one heatsink to dissipate heat and to provide an electrical connection, at least a first system for clamping the power semiconductor components, at least a second system for clamping components protecting the power semiconductor components, at least one spacer for insulating the semiconductor components from the framework of the various modules and at least one conductive block replacing heatsinks that are rendered unnecessary by the arrangement chosen for the inverter and auxiliary chopper functions.

Abstract: A sensor (10,30) is formed that does not require a bonding process in an oxygen rich or vacuum ambient. In a first embodiment, a port (14), a channel (15) and an opening (18) are used to provide an oxidizing ambient to a cavity (13). During an oxidation process, the cavity (13) is sealed and any remaining oxidizing ambient is consumed to form a sealed cavity that is under a vacuum pressure. In an alternate embodiment, a cavity (32) is formed in a first substrate (31). The cavity (32) is covered by a second substrate (36) and an opening (33,34) is formed in the second substrate (36) above the cavity (32). These openings (33,34) allow an oxidizing ambient to enter the cavity (32).

Abstract: Disclosed is a method for making a passivation coated semiconductor structure. The method includes providing a substrate having a metallization line patterned over the substrate. The metallization line defining at least one interconnect feature having a first thickness, and depositing a first silicon nitride barrier layer having a second thickness over the substrate and the metallization line. The method further including applying an oxide material over the first silicon nitride barrier layer that overlies the substrate and the metallization line. The oxide application includes a deposition component and a sputtering component, and the sputtering component is configured to remove at least a part of an edge of the first silicon nitride layer. The edge is defined by the metallization line underlying the first silicon nitride layer.

Abstract: An asymmetric snubber resistor in accordance with the present invention includes a cathode, an N+ region, an N- region, a plurality of P+ regions, and an anode. The N+ region is disposed over the cathode, the N- region is disposed over the N+ region, the plurality of P+ regions are disposed over the N- region, and the anode is disposed over the plurality of P+ regions and exposed portions of the N- region. The asymmetric snubber may also include N regions between the P+ regions. The asymmetric snubber resistor replaces the snubber diode and the snubber resistor in a typical snubber circuit.

Abstract: A packaged semiconductor device, such as a lead frame device, includes a circuit supported within an enclosure. The circuit is coupled to a plurality of conductive leads within the enclosure. The leads extend from the enclosure for electrically coupling the circuit to external circuitry. At least one of the leads is shielded to reduce inductive coupling and crosstalk between the leads during high frequency switching. The shielded lead has a conductive base, a non-conductive layer disposed on the base, and a conductive layer disposed on the non-conductive layer. The non-conductive and conductive layers may be formed prior to electrically coupling the lead to the circuit, or following assembly of the lead frame package. The shielding may extend into the package enclosure, or may terminate external to the enclosure.

Abstract: A socket terminal assembly includes a socket body having an end with an opening and an opposite end configured to contact the corresponding connection region of a printed circuit board, a contact spring, disposed at the opening of the socket body, to receive and apply a frictional force sufficient to retain the lower end of a pin within the opening of the socket body; and a resilient member, disposed within a lower end of the opening, to apply, to the pin and in response to a downward force applied to the pin, an upward force sufficient to overcome the frictional force of the contact spring. The pin has an end adapted to contact an electrical contacting area of an integrated circuit package and an opposite end configured to be inserted within the opening of the socket body. An intercoupling component includes a socket support member having holes, each hole receiving a corresponding socket terminal assembly.

Abstract: A semiconductor package is provided that has a rigid metal substrate and a dielectric layer covering a first portion of the rigid metal substrate, with a second portion of the rigid metal substrate being substantially free of the dielectric layer. A semiconductor device is electrically bonded to the second portion of the rigid metal substrate and metal circuit traces defining electrical paths are formed on the dielectric layer, at least one of which contacts the rigid metal substrate through at least one via in the dielectric layer. Additionally, a method is provided for grounding a semiconductor device and at least one circuit trace on a rigid metal substrate substantially covered by a dielectric layer, which includes creating at least one via in the dielectric layer using a laser and creating circuit traces on the dielectric layer, at least one of which contacts the rigid metal substrate through at least one of the vias.

Abstract: The semiconductor package for improving the efficiency of spreading heat and the capability of electrical function is disclosed. A semiconductor die is attached on the BT substrate by using a conventional die attaching material. The die is electrically coupled to conductive traces on the top surface of the substrate by the bonding wires, a TAB method or a flip chip method. A plurality of conductive vias are also need for electrically coupling conductive traces on the top surface of the substrate to those on the bottom. At an end portion of each conductive trace on the bottom of the substrate is an conductive pad for connecting to a solder ball for transferring electrical signal. A heatspreader is exactly set over the semiconductor die for improve the efficiency of spreading heat. Additionally, the heatspreader is connected on the ground land of the substrate via a conductive adhesives to form a ground plane.

Abstract: The semiconductor storage device comprises memory cell transistors formed on a semiconductor substrate 10; first insulation films 42 covering the top surfaces and the side surfaces of gate electrodes 20 of the memory cell transistors; through-holes 40 opened on first diffused layers 24; a second insulation film 36 with through-holes 40 opened on first diffused layers 24 and through-holes 38 opened on second diffused layers 26 formed in; capacitors formed on the inside walls and the bottoms of the through-holes 40 and including capacitor storage electrodes 46, connected to the first diffused layers 24; capacitor dielectric films 48 covering the capacitor storage electrodes 46, and capacitor-opposed electrodes 54 covering at least a part of the capacitor dielectric films 48; and, contact conducting films 44 formed on the inside walls and bottoms of the through-holes 38, and connected to the second diffused layers.

Abstract: A solder ball land metal structure of a ball grid array semiconductor package capable of obtaining a maximum contact area between a solder ball land metal element and a solder ball fused on the land metal element. A solder mask defined type land metal structure according to the present invention has a single etching hole at the central portion thereof or a plurality of etching holes at the outer portion thereof in order to obtain an increased contact area for a solder ball. Each etching hole extends from the upper surface of the land metal element to the upper surface of the BT substrate throughout the land metal element or extends from the upper surface of the land metal element to a depth corresponding to about half the thickness of the land metal element. Each etching hole serves as a locking hole for fixing the fused solder ball. Thus, it is effectively prevent the solder ball from being separated from the land metal element.

Abstract: A semiconductor strain sensor has a gauge forming region on a p-type substrate surrounded by a p-type isolation region that reaches the p-type substrate. The p-type substrate is etched so that the entire bottom surface of the gauge forming region is covered by the p-type substrate, and the p-type substrate or p-type isolation region is not exposed to the etched recess portion or isolation groove, each of which have a relatively high number of defects. Thus, leakage current at the PN junction can be decreased to decrease a variation in the potential of the gauge forming region.

Abstract: Control gate electrodes 12 are formed on field oxidation layers 19. Anisotropic etching is carried out by covering all the regions except for a source region by photo-resist layers 31 and using the control gate electrodes 12 as a mask. Concave parts 20 are formed in the inner side of the control gate electrodes 12 of the field oxidation layer 19. A source region 4b is formed by carrying out ion implantation. Drain regions 3 and a source region 4 are formed by removing the photo-resist layers 31, and by carrying out ion implantation using the control gate electrodes 12 as a mask. The source region is formed by removing a part of the isolation region positioned adjacently to the source region located in a peripheral part of the control gate electrodes 12. As a result, it is possible to reduce the distance between two of the control gate electrodes positioned adjacently as well as increasing integration level of the nonvolatile memory devices.

Abstract: A semiconductor device comprises a plurality of solder bumps each formed on a pad of a semiconductor device. The top of each of the solder bumps is covered with a masking film, and the bases of the solder bumps are buried with a reinforcement film. The oxidation of the solder bumps is prevented by the masking film and the reinforcement film, the latter also undertaking the thermal stress generated between the semiconductor chip and the circuit board. The mounting is conducted with the masking film remaining on the top of the solder ball, which breaks the masking film and connected to the pad on the circuit board.