Abstract: A semiconductor device and a method of manufacturing the same provide a structure which can be easily integrated to a higher extent without providing an alignment margin taking an alignment accuracy of photolithography into consideration. In the semiconductor device, a gate electrode and a pair of source/drain electrodes are formed inside a transistor opening formed at first and second insulating films forming a flat element isolating film. Thereby, an end of the gate electrode in the width direction is defined in an aligned manner by the transistor opening in the step of forming the gate electrode so that it is not necessary to provide the alignment margin taking the alignment accuracy into consideration. This allows high integration.

Abstract: Composite TiO.sub.2 /Ta.sub.2 O.sub.5 films by in-situ sequential CVD deposition are presented for a storage capacitor of a three-dimensional cell in DRAM applications. The capacitor with the Ta.sub.2 O.sub.5 /TiO.sub.2 /Ta.sub.2 O.sub.5 alternating layer structure has comparable leakage current density and higher capacitance per unit area as compared to a capacitor with Ta.sub.2 O.sub.5 and TiO.sub.2 single layer structures.

Abstract: A semiconductor light emitting device includes at least two semiconductor light emitting elements which emit different colors of light to each other. The device further includes a lead frame for supporting the light emitting elements and a resin molding for sealing these elements. The external form of this resin molding is an ellipsoid or a part of an ellipsoid in which the curvature in the perpendicular direction to the element row is designed to be smaller than that in the parallel direction to the row. As a result, the device has a widely spread mixed color range especially in the perpendicular direction to the element row and high luminous intensity especially in the parallel direction to the element row. So, a multicolor light emitting device having a high ability of color mixture as well as high luminous intensity can be obtained.

Abstract: It is an object to enhance accuracy of intervals and parallelism between signal pins and guide pins. Guide pins (5) are integrally united to outsert cases (9) made of resin to which signal pins (3) are planted. The outsert cases (9) are fixed to a circuit board (6) and the signal pins (3) and the guide pins (5) are thus fixed to the common circuit board (6), so that the accuracy of intervals and parallelism among them is high. The circuit board (6) is accommodated in a box-like case and the opening of the case is covered with a lid (4). The guide pins (5) and the signal pins (3) pass through holes (21, 22) provided in the lid (4) and project to the outside. The guide pins (5) play a role of guiding the signal pins (3) when the signal pins (3) are coupled to an external connected body. At the same time, the guide pins (5) also serve to guide the signal pins (3) into the holes (22) when the lid (4) is mounted, so that the workability in the manufacturing process is enhanced.

Abstract: A connecting device, and corresponding method, for connecting a semiconductor chip/chip and a conductor, the connecting device including: a pad formed on the chip; a passivation layer formed around the pad thereby defining an aperture in the passivation layer; a pad-to-bump connecting layer at least in the aperture; and a bump, formed on the pad-to-bump connecting layer, not extending laterally outside of the aperture. The passivation layer is also formed on an edge area of the pad so as to define shoulder portions between which the aperture is located. The pad-to-bump connecting layer includes: a first base layer formed in the aperture and also on the shoulder portions of the passivation layer so that the first base layer extends laterally outside the aperture; and a second base layer formed at least in the aperture. The cross-sectional area of the bump is less than the cross-sectional area of the aperture.

Abstract: Contact pads for providing external electrical connection to components on a radiation imager having a photosensor array include a body of the material utilized for fabrication of the photosensors with an indium tin oxide (ITO) top layer disposed over the photosensor material to provide a contact region. A metal contact surface can also be disposed over the ITO. A barrier dielectric material is further disposed over portions of the contact pad.

Abstract: A circuit for protecting a bonding pad of a semiconductor device from ESD voltages is located under the pad to permit the space otherwise used for a protection circuit to be used for normal operating components. The protection circuit has a compact layout that provides maximum ability to handle an ESD current within this limited space. The semiconductor structure for the circuit has separate parts for two SCR circuits, one for each polarity of ESD current. Each SCR circuit comprises two symmetrical SCR structures.

Abstract: A lid for a chip/package system includes a body sized to fit over an integrated circuit chip and being connectable to a package. The body has at least two regions exhibiting different coefficients of thermal expansion, with one CTE matching that of the chip and the other matching that of the package.

Abstract: An image forming system utilizing a light emitting diode (LED array) having LEDs arranged along a curved line. The LEDs are either edge emitting type LEDs or surface emitting type LEDs. The LEDs of the LED array emit light towards a center or optical axis of the lens. A plurality of lenses are connected together to form a lens array. Alternatively, two lens arrays can be utilized. If two lens arrays are utilized, each of the lenses in the lens array includes an aspherical surface. The curved LED array prevents the flaring of light and produces an even pattern of light emission on a light receiving surface such as a photoconductive drum.

Abstract: The object of the present invention is to provide a multichip IC card which seems to be a single chip IC card constituted by one chip and in which plural function chips are built. The multichip IC card is provided with a connector 3 for connecting to an interface processor 1, a master chip 4 for controlling a system in a card, at least one function chip 6-1 to 6-n and selection means 5A for connecting the function chip selected by the master chip and the interface processor 1 via the connector 3.

Abstract: Time coefficient .beta., voltage coefficient d and temperature coefficient .phi..sub.0 of a jumbo TFT including a plurality of TFTs connected parallel to each other and manufactured under the same condition are obtained through experiment using -BT stress test, mean value .mu. and standard deviation .sigma. of the threshold voltage shift amount are calculated by -BT stress test for a plurality of individual TFTs, and the life t of the individual TFT is evaluated by the expression.

Abstract: The present invention provides methods of producing an anti-reflective layer on a semiconductor wafer/device and wafers/devices including that anti-reflective layer. The anti-reflective layer is produced by annealing layers of titanium and aluminum on a wafer/device to provide a roughened surface that significantly reduces reflectivity to improve the accuracy and definition provided by optical lithography processes.

Abstract: The electronic device has a structure that a semiconductor package (10) is mounted on a motherboard (21), and a buffer layer (41) for relieving a stress, which is produced due to a difference of physical properties between the semiconductor package (10) and the motherboard (21), is mounted on the electrical and mechanical interface between the semiconductor package (10) and the motherboard (21). For example, the buffer layer (41) having a thermal expansion coefficient close to that of the motherboard (21) is formed on a face of the semiconductor package 10 having an external connecting terminals (12b) mounted. A stress caused due to a difference between a thermal expansion coefficient of a wiring substrate (12) of the semiconductor package and that of the motherboard (21) can be relieved by the buffer layer (41).

Abstract: A semiconductor die is disposed on a side of an optically-transmissive preformed planar structure (interposer), and an optical element is disposed on an opposite side of the interposer. The interposer may be provided with through holes extending at least partially into the die side, and electrical probes in the through holes, for making contact to raised conductive bumps on the die. The interposer may be provided with raised portions for locating the optical element at a predetermined distance away from the die. The interposer may be provided with darkened areas for preventing light from impacting selected areas of the die.

Abstract: An electrical component has a chip body made of resin, and a metallic pattern including a plurality of terminals to be bonded to a printed circuit, a plurality of interconnects extending on the top surface and connected to the terminals. The chip body has a plurality of small thickness region each corresponding to one of the interconnects. Each of the small thickness regions can be selectively broken after bonding the chip body onto a printed circuit board by a thrusting tool for disconnection. The chip body can provide a desired function of the electronic circuit after fabrication of an electronic device.

Abstract: A semiconductor device with reduced thickness, improved heat radiation, and a stacked structure. Molded resin covers an IC chip wire and part of a die pad. The die pad is exposed from the molded resin. An external lead in the same plane as the exposed surface of the die pad extends to a side of the resin opposite the die pad and along the molded resin. This structure allows a reduction in thickness of the semiconductor device, the exposed die pad improves heat radiation, and the external lead on upper and lower surfaces of the resin allows the semiconductor devices to be stacked.

Abstract: An LOC semiconductor package includes: a semiconductor chip; a plurality of two-sided tapes being attached on predetermined portions of the semiconductor chip inthe form of layers; a lead frame having a step coverage corresponding to the form of the two-sided tape; wires electrically connecting inner leads of the lead frame to pads of the semiconductor chip; and a coating fluid for covering the semiconductor chip, the lead frame and the wires. Its fabricating method includes the steps of: forming an LOC lead frame having dam bars for a chip size package; attaching a plurality of two-sided tapes on the dam bars of the lead frame in the form of layers; attaching a semiconductor chip onto an uppermost layer of said plurality of two-sided tapes; wire-bonding a pad of the semiconductor chip to respective inner leads of the lead frame by using a conductive means; and potting to inject a coating fluid into the lead frame.

Abstract: An integrated circuit with high density pad structures is provided. The circuit has circuitry covered by an insulating layer. Pads are formed on the insulating layer overlapping the circuitry. A pattern of holes in the insulating layer allows electrical connections to be formed between the pads and the underlying circuitry. Because the pads are formed on top of the circuitry, the die area occupied by pads is reduced relative to the die area occupied by circuitry. The pads are suitable for flip-chip bonding to a package such as a multichip module or conventional wire bonding.

Abstract: A void is defined between adjacent wiring lines to minimize RC coupling. The void has a low dielectric value approaching 1.0. For one approach, hollow silicon spheres define the void. The spheres are fabricated to a known inner diameter, wall thickness and outer diameter. The spheres are rigid enough to withstand the mechanical processes occurring during semiconductor fabrication. The spheres withstand elevated temperatures up to a prescribed temperature range. At or above a desired temperature, the sphere walls disintegrate leaving the void in place. For an alternative approach, adjacent wiring lines are "T-topped" (i.e., viewed cross-sectionally). Dielectric fill is deposited in the spacing between lines. As the dielectric material accumulates on the line and substrate walls, the T-tops grow toward each other. Eventually, the T-tops meet sealing off an internal void.

Abstract: An Ion-sensitive Field Effect Transistor (ISFET) sensor for sensing ion activity of a solution includes a substrate and an ISFET semiconductor die. The substrate has front surface exposed to the solution, a back surface opposite to the front surface and aperture extending between the front and back surfaces. The ISPET semiconductor die has an ion-sensitive surface with a gate region. The ion-sensitive surface is mounted to the back surface such that the gate region is exposed to the solution through the aperture.