Abstract: One end of bonding wires made of aluminium, gold, etc., is connected to a plurality of electrode pads formed on the main surface of a semiconductor chip. The other end of these bonding wires is exposed on the surface of the molded resin unit. Connecting electrodes made of aluminium are formed on top of the exposed parts of these bonding wires. The semiconductor chip and external circuitry are connected electrically by means of these connecting electrodes.

Abstract: A wiring layer of a semiconductor device having a novel contact structure is disclosed. The semiconductor device includes a semiconductor substrate, an insulating layer having an opening (contact hole or via), a reactive spacer formed on the sidewall of the opening or a reactive layer formed on the sidewall and on the bottom surface of the opening and a first conductive layer formed on the insulating layer which completely fills the opening. Since the reactive spacer or layer is formed on the sidewall of the opening, when the first conductive layer material is deposited, large islands will form to become large grains of the sputtered Al film. Also, providing the reactive spacer or layer improves the reflow of the first conductive layer during a heat-treating step for filling the opening at a high temperature below a melting temperature. Thus, complete filling of the opening with sputtered Al can be ensured. All the contact holes, being less than 1 .mu.m in size and having an aspect ratio greater than 1.

Abstract: Memory devices, such as random access memory, are affixed to an electrical contact frame and coupled to signals lines on the contact frame which is, in turn, mounted on a top surface of an integrated circuit. The signal leads are coupled to electrical contact pads disposed on the top surface of the integrated circuit. The contact pads and signal leads transfer control and power signals between the integrated circuit and the memory devices.

Abstract: A method and apparatus for dissipating heat from a semiconductor device. A heat sink embodying the method includes an exterior surface contoured to better facilitate heat dissipation and/or direct a flow of air or fluid over the heat sink. In one embodiment, the heat sink includes a heat sink layer formed from a powdered metal. In another embodiment, the heat sink layer is contoured with a selected combination of bumps, indentations and holes. In yet another embodiment, the heat sink includes a stack of such heat sink layers which are mechanical; interfitted and thermally coupled.

Abstract: A semiconductor package comprises a circuit board having a wiring circuit including at least a connecting portion, the wiring circuit being formed on a first main surface of the circuit board, a semiconductor chip mounted on the first main surface of the circuit board on face-down basis, an insulation resin layer filled in a space between the semiconductor chip and the circuit board, and a flat-type external connecting terminal electrically connected to the semiconductor chip and formed and exposed to a second main surface of the circuit board.

Abstract: A semiconductor device formed on a semiconductor substrate includes a layer which is substantially a barrier to hydrogen formed on the semiconductor substrate. A plug, formed of a material through which hydrogen can diffuse, is disposed in an opening through the layer and contacts a surface of the semiconductor substrate. Hydrogen may be diffused into the semiconductor substrate through the plug.

Abstract: Spin-on HSQ is employed to gap fill metal layers in manufacturing a high density, multi-metal layer semiconductor device. The degradation of deposited HSQ layers during formation of borderless vias, as from photoresist stripping using an O.sub.2 -containing plasma, is overcome by treating the degraded HSQ layer with an H.sub.2 -containing plasma to restore the dangling Si--H bonds, thereby passivating the surface and preventing moisture absorption, before filling the via opening with conductive material, such as a barrier layer.

Abstract: A low dielectric insulation layer for an integrated circuit structure material, and a method of making same, are disclosed. The low dielectric constant insulation layer comprises a porous insulation layer, preferably sandwiched between non-porous upper and lower insulation layers. The presence of some gases such as air or an inert gas, or a vacuum, in the porous insulation material reduces the overall dielectric constant of the insulation material, thereby effectively reducing the capacitance of the structure. The porous insulation layer is formed by a chemical vapor deposition of a mixture of the insulation material and a second extractable material; and then subsequently selectively removing the second extractable material, thereby leaving behind a porous matrix of the insulation material, comprising the low dielectric constant insulation layer.

Abstract: A battery mounted integrated circuit device comprises a semiconductor chip in which an integrated circuit including a plurality of power receiving circuits with different operating voltages is formed; a thin film laminated battery made of a solid electrolytic film mounted on the semiconductor chip for producing a plurality of voltages; and a power source switch incorporated in said integrated circuit for connecting said battery to the power receiving circuits to supply the plurality of voltages from the battery to the power receiving circuits on demand.

Abstract: A SQUID 10 was multiple junctions, each junction allowing a critical current to flow therethrough. The SQUID 10 comprises a laminar structure including: (a) a substantially planar substrate 12; (b) a first high temperature superconductive layer 14 of substantially uniform thickness deposited on the substrates; (c) a dielectric layer 16 deposited on the first superconductive layer 14, the dielectric layer 16 comprising a planar level segment 18 having two ramp segments defining SQUID junctions at opposing ends 20 and defining SQUID hole; and (d) a second high temperature superconductive layer 24 of substantially uniform thickness deposited on the dielectric layer 16, the second high temperature superconductive layer 24 covering all three segments of the dielectric layer 16.

Abstract: Stacked die that are separated by an overlaying chip capacitor with a plate bonded to the bottom of the top die with a conductive adhesive and the capacitor shell bonded to the top of the lower die with a non-conductive adhesive. The lower die is attached to a substrate using a conductive adhesive. Conductors extend from edge terminals on the substrate to edge terminals on the lower die, and conductors extend from the lower die terminals to the capacitor that are tiered to provide space between the die for the wires and connections. A second overlaying capacitor is attached to the top of the upper die with non-conducive adhesive. Pads on the capacitor are connected by conductors to edge pads on the die and conductors extend from the pads to pads on the substrate.

Abstract: A MOS transistor includes a void space as part of the gate oxide layer on the drain end of the transistor. The void space replaces a region of the gate oxide layer so that no oxide is present for injection of hot carriers. The presence of the void space, preferably containing a vacuum, also reduces the total gate capacitance of the device. The void space is formed by chemical etching of the gate oxide layer and void space sealing during device manufacture.

Abstract: A nonlinear resistance element of this invention comprises a first conductive layer, an insulating layer, and a second conductive layer stacked in sequence on a substrate, wherein: the first conductive layer is a metal film whose main component is a metal to which is added a chemical element having a valence 1 or 2 greater than that of the main component metal, in a concentration of 0.2% to 6 atom %, and the insulating layer is an anodized layer of the first conductive layer. This nonlinear resistance element is particularly suitable for use as a switching element for an active matrix type of liquid crystal display device.

Abstract: The tungsten nitride film containing fluorine is used as a barrier metal in the contact hole or via hole of the semiconductor device. The tungsten nitride film formed contains 1% to 20% fluorine at atomic density. With this structure, it is possible to obtain a WNF film having a good step coverage for a fine hole.

Abstract: In an LSI package, terminal resistance elements are formed of resistive paste which, consisting of a mixture of fine powder of either oxidized metal or carbon and fine powder of glass, is buried and sintered in a ceramic wiring board in the direction to penetrate it. Front side wiring, connecting the parts of the terminal resistance elements exposed on the front face of the ceramic wiring board to input/output circuits of the LSI chip to be mounted on the front face of the ceramic wiring board, is formed on the front face of the ceramic wiring board and in the top layer of the ceramic wiring board. Back side wiring, connecting the parts of the terminal resistance elements exposed on the back face of the ceramic wiring board to a voltage clamp wiring network, is formed on the back face of the ceramic wiring board.

Abstract: The semiconductor device of the present invention is equipped with a plurality of photodiodes, a horizontal transfer part and a vertical transfer part, and in particular, the horizontal transfer part or the vertical transfer part has a configuration described as in the following. Namely, the device has a semiconductor region which is formed by regularly and consecutively arranging a plurality of blocks of the same conductivity type, where each of the plurality of the blocks is equipped with three regions of mutually different impurity concentrations, clock pulses are applied to two regions out of the three regions and the voltage of the high level or low level of the clock pulse is applied to the remaining region out of the three regions as a constant potential.

Abstract: A photonic device according to the present inventions obtained by resin molding a photonic element mounted on a base using a light-transmitting resin wherein the cured hardness of the light-transmitting resin is set at a value for optimally minimizing the adhesion of dust particles on the surface of the light-transmitting resin and the generation rate of internal cracks of the light-transmitting resin for a predetermined temperature change on the basis of the correlation between the two. A process for fabricating a photonic device according to the present invention comprises resin molding a photonic element by potting a light-transmitting resin having a predetermined viscosity, and applying a predetermined heat treatment for curing the resin to a final hardness after driving out the bubbles from the inside of the light-transmitting resin and for relaxing the curing shrinkage stress.

Abstract: Disclosed is an optical and/or microelectronics hermetic package which includes a member for absorbing hydrogen from the internal package ambient. The member includes a first layer which forms a hydride and, formed thereover, a second layer which forms solvated hydrogen upon exposure to molecular hydrogen in the package. The second layer acts as a one way valve for transporting hydrogen to the first layer which locks up the hydrogen.

Abstract: In a multilevel interconnection structure for a semiconductor device, lower level interconnections 3 are formed on an insulator film 2 formed on a substrate 1, and a silicon oxide film 4a is formed to cover the lower level interconnections 3 and to fill up a region between adjacent lower level interconnections 3, by means of a biased ECR-CVD process so that a cavity 5 is formed in the silicon oxide film 4a between the adjacent lower level interconnections 3. The silicon oxide film 4a is selectively removed from a tolerable region covering the extent in which a hole for the metal pillar 6 is allowed to deviate from a target lower level interconnection 3, and then, another silicon oxide 4b is formed to fill up the removed portion and to cover the first silicon oxide film. The metal pillar 6 is formed to extend through the silicon oxide film 4b filling the removed portion of the silicon oxide film 4a, so as to reach the target lower level interconnection 3.

Abstract: A method of manufacturing an SRAM cell with polysilicon diode loads using standard logic technology processing. A P+ polysilicon area and an N+ polysilicon are forms a lateral PN junction. In standard logic technology processing the lateral PN junction is shorted out. In the present invention the lateral PN junction is allowed to function as a polysilicon diode load and an ancilliary lateral PN junction is shorted using a polycide cap layer.