Abstract: A nondestructive inspection apparatus having a SQUID is made with compact configuration and is capable of detecting a metallic or non-metallic metal for defects, corrosion, and the like, by forming the SQUID and a magnetic field applying coil on the same substrate. The SQUID comprises two Josephson junctions, a washer coil connected to the Josephson junctions to form a superconducting loop, shunt resistors, a damping resistor, and a feedback modulation coil, all of which are formed from a superconducting thin film on a supporting substrate. A magnetic field applying coil is formed on the same supporting substrate with a superconducting thin film or a normal conducting metal thin film. The magnetic field applying coil, which generally has plural turns around the SQUID, applies a dc or ac magnetic field to a sample. The change in magnetic field caused by a defect in the sample is detected by the washer coil, and the position and size of the defect may thus be determined.

Abstract: After forming a first wire on a first interlayer insulation film, a second interlayer insulation film is formed and planarized, to thereby form a via hole. At this stage, the via hole is formed off the first wire. Next, after making an exposed edge and an exposed side wall of the first wire slanted surfaces, a second wire is formed with or without a conductive film buried within the via hole. Since the side wall of the first wire is a slanted surface in this manner, it is possible to completely bury a wire material of the second wire or the conductive film within the via hole, and therefore, it is possible to ensure electric conduction all over the slanted surfaces of the first wire. As a result, even if the via hole which connects the first wire in a lower layer and the second wire in an upper layer is formed of f the first wire, an increase in a wire resistance in the via hole is prevented.

Abstract: A single mask, low temperature reactive ion etching process for fabricating high aspect ratio, released single crystal microelectromechanical structures independently of crystal orientation.

Abstract: A semiconductor chip package comprises a chip attach pad having a slot formed in a perimeter region thereof. A chip having input/output pads thereon is bonded with the chip attach pad, and leads corresponding to the input/output pads are arranged around the chip. Each lead is electrically coupled to each input/output pad by a bonding wire. The chip, the chip attach pad, bonding wires, and leads are encapsulated by a molding compound. The slot of the chip attach pad corresponds to edges of the chip, so that the lower surface edges of the chip are located along the slot and are exposed through the slot. The molding compound is contained within the slot of the chip attach pad, and adheres to the lower surface edges of the chip. Accordingly, failures such as delaminations or cracks can be prevented. The slot may be divided into several discrete slots, and a tie-bar may be joined to the chip attach pad.

Abstract: A memory array of PROM, EPROM or EEPROM cells has each cell formed in a trench of a thick oxide layer deposited on a silicon substrate, in a manner that a significant portion of opposing areas of the floating gate and control gate of each cell which provide capacitive coupling between them are formed vertically. This allows the density of the array to be increased since the amount of semiconductor substrate area occupied by each cell is decreased without having to sacrifice the amount or quality of the capacitive coupling. Further, a technique of forming capacitive coupling between the floating gate and an erase gate in a flash EEPROM array cell with improved endurance is disclosed.

Abstract: An n-type epitaxial layer is formed on a main surface of a p-type silicon substrate. An n-type buried diffusion layer is formed extending in both the p-type silicon substrate and the n-type epitaxial layer. An n-type diffusion layer is formed in the surface of the n-type epitaxial layer, which is disposed above the n-type buried diffusion layer. A p-type diffusion layer is formed so as to surround side ends of the n-type diffusion layer. A p-type buried diffusion layer is formed so as to have a bottom face within the n-type buried diffusion layer and have side ends thereof inside side ends of the p-type diffusion layer. A collector region of a vertical pnp bipolar transistor consists of the p-type buried diffusion layer and the p-type diffusion layer. A p-type diffusion layer, which serves as an emitter region of the pnp bipolar transistor, is formed in the surface of the n-type diffusion layer.

Abstract: This invention provides an improved porous structure for semiconductor devices and a process for making the same. This process may be applied to an existing porous structure 28, which may be deposited, for example, between patterned conductors 24. The method may comprise providing a substrate comprising a microelectronic circuit and a porous silica layer, the porous silica layer having an average pore diameter between 2 and 80 nm; and heating the substrate to one or more temperatures between 100 and 490 degrees C. in a substantially halogen-free atmosphere, whereby one or more dielectric properties of the porous dielectric are improved. In some embodiments, the atmosphere comprises a phenyl-containing atmosphere, such as hexaphenyldisilazane.

Abstract: A method of forming a thick interlevel dielectric layer containing sealed voids formed in a controlled manner, over a substantially planar surface in semiconductor device structure, and the semiconductor structure formed according to such a method. The sealed voids are used to reduce interlevel capacitance. A plurality of metal signal lines are formed over a globally planarized insulator. A thick layer of first conformal interlevel dielectric is deposited over the metal signal lines and over the intermetal spacings formed between the metal signal lines. Because of the thickness, flow properties, and manner of deposition of the interlevel dielectric and the aspect ratio the intermetal spacings, voids are formed in the first conformal interlevel dielectric, in the intermetal spacings. This interlevel dielectric is then etched or polished back to the desired thickness, which exposes the voids in the wider intermetal spacings, but does not expose voids in the narrower intermetal spacings.

Abstract: A process and resulting structure are described for using a metal layer formed over an insulating layer as both the filler material to fill openings in the insulating layer and as the patterned metal interconnect or wiring harness on the surface of the insulating layer. The process includes the steps of forming a compressively stressed metal layer over an insulating layer having previously formed openings therethrough to the material under the insulating layer; forming a high tensile strength cap layer of material over the compressively stressed metal layer; and then heating the structure to a temperature sufficient to cause the compressively stressed metal layer to extrude down into the openings in the underlying insulating layer. The overlying cap layer has sufficient tensile strength to prevent or inhibit the compressive stressed metal layer from extruding upwardly to form hillocks which would need to be removed, i.e., by planarization.

Abstract: A semiconductor device includes a groove formed in a surface of a first semiconductor substrate of one conductivity type in order to partition and isolate first and second device regions. A first insulating film on the first semiconductor substrate of the first device region also contacts the groove. A second insulating film covers an inner wall of the groove. The first insulating film is thicker than the second film in order to increase the breakdown voltage and facilitate carrying a higher current. This thickness relationship also aids manufacturing.

Abstract: A method for fabrication of metal to semiconductor contacts results in sloped sidewalls in contact regions. An oxide layer is deposited and etched back to form sidewall spacers. A glass layer is then deposited and heated to reflow. After reflow, an etch back of the glass layer results is sloped sidewalls at contact openings and over steps.

Abstract: In order to reduce the chip size of a semiconductor device as well as to separate noises between at least two types of pads having different functions, at least one Vcc and at least one Vss are provided on opposite edges of a package (101) so that output pins or I/O pins are arranged therebetween and input pins are arranged outside the same. Non-connected excess pins (NC) are arranged on upper and lower boundaries, for omitting wires and reducing the chip size.

Abstract: Heat sinks and methods particularly suited for use on packaged integrated circuits which are not amenable to the use of snap-on heat sinks and on which cemented-on heat sinks prevent conventional probing or reworking of the integrated circuit in the event trouble-shooting of the circuit is required after mounting of the heat sink. In accordance with the invention, a scalable post, based on heat sink size, mass and integrated circuit size, is cemented to the integrated circuit package in a configuration and location not interfering with the later probing or reworking of the integrated circuit, and without interfering with the printed circuit board layout. The post is then used to removably and independently hold a heat sink onto the integrated circuit so that good heat transfer between the integrated circuit and the heat sink is achieved, but still allowing the removal of the heat sink at any time if probing of the integrated circuit is later required. Alternate embodiments are disclosed.

Abstract: A semiconductor device having a multilayer interconnection structure, includes a substrate having a metal interconnect layer provided thereon and N number (N being an integer of 2 or greater) of layers of insulating film formed one on top of another on the substrate. Each layer of insulating film has a metal interconnect layer including at least one bonding pad section provided thereon. At least one via hole filled with an electrically conductive material is provided in each of the layers for interconnecting metal interconnect layers. At least one bonding pad connecting hole filled with an electrically conductive material is provided in each of the layers for interconnecting bonding pad sections. The at least one bonding pad connecting hole is no more than twice as large in diameter as a smallest via hole.

Abstract: A high melting point metal wiring layer, a second aluminum wiring layer, and a third aluminum wiring layer are stacked on transistors forming an inverter train of a hierarchical power supply structure respectively. The high melting point metal wiring layer is employed as a local wire for connecting the transistors with each other, the second aluminum wiring layer is employed as a local bus wire and a hierarchical power supply wire, and the third aluminum wiring layer is employed as a main bus wire and a power supply wire to intersect with the respective wires. Consequently, the wiring layers are easy to lay out, while no main bus region is required dissimilarly to the prior art and it is possible to reduce the layout area.

Abstract: A semiconductor acceleration sensor of a single integral type has a semiconductor substrate, a first nitride layer, a first poly-silicon layer, a second nitride layer, a second poly-silicon layer, a third nitride layer and a third poly-silicon layer which are fabricated in order. A movable section is formed in a part of the second poly-silicon layer placed in a cavity enclosed and sealed by the first nitride layer, the first poly-silicon layer, the second nitride layer, the second poly-silicon layer, the third nitride layer and the third poly-silicon layer. A fabrication method of the semiconductor acceleration sensor of a single integral type is also disclosed.

Abstract: A microelectronic assembly (10) includes an integrated circuit component (14) attached to a polymeric substrate (12) by a plurality of unencapsulated solder bump interconnections (16). A collar (18) is affixed to the polymeric substrate (12) about the integrated circuit component (14) and is formed of an inorganic material having a coefficient of thermal expansion less than that of the substrate (12). The collar (18) constrains thermal expansion of the polymeric substrate (12) in the die attach region (22), thereby lessening any deleterious effects caused by a mismatch in the thermal expansion of the polymeric substrate (12) and the integrated circuit component (14).

Abstract: An electronic fingerprint sensor works by the detection of pressure, the ridge lines of the finger exerting a greater pressure than the valleys. The sensor has a matrix of pressure microsensors and electronic control and signal-processing circuits. It is made in an entirely monolithic form, according to techniques for the making of electronic circuits (deposition of thin layers, photo-etching, doping and thermal processing), both for the pressure detection part and for the signal-processing and control part. The matrix-type pressure sensor uses either piezoelectric resistors lying on an insulator layer stretched above a cavity or a variable capacitor or a microcontactor.

Abstract: A photosensitive device, e.g. for use as an optical sensor for a video camera, is designed to capture light and to deliver an electrical signal representative of the captured light, and presenting a resistance to hard electromagnetic radiation. The device includes a photosensitive element in hydrogenated amorphous silicon and a collector for the electrical charges induced by the photoelectric effect in the photosensitive element capturing the light and for delivering an electrical signal resulting therefrom. The device is electrically connected to an electronic processor for processing the electrical signal.

Abstract: A semiconductor device comprises a chip soldered to a support. The chip comprises a semiconductor substrate, a via a ground plane on a rear surface, and an anti-adhesion layer deposited continuously inside the via. A solder layer which does not wet the anti-adhesion layer but which does wet the ground plane has a globular shape in the via opening and makes no mechanical contact with the walls of the via. The manufacturing process comprises the sandwiching of a soldering preform between the support and the rear surface provided with the ground plane and said anti-adhesion layer, and melting of the preform under pressure so that the solder rises in globular shape inside the via. The anti-adhesion layer is realized without mask.