Abstract: In a semiconductor device, a metal oxide semiconductor (MOS) transistor is formed on a semiconductor substrate to have a gate electrode which is formed on a gate oxide film. The first insulating layer is formed to cover the semiconductor substrate and the MOS transistor. The second insulating layer is formed to cover the first insulating layer. The first wiring structure is formed on the first insulating layer. A part of the first wiring structure passes through the second insulating layer. The second wiring structure is not connected to the first wiring structure, and passes through the first and second insulating layers to be connected to the gate electrode. The second wiring structure has an antenna ratio of equal to or less than 1000. The third wiring structure is connected to the first and second wiring structures and formed on the second insulating layer to have the antenna ratio of equal to or less than 1000.

Abstract: A semiconductor device (10) having a stacked-gate buffer (30) wherein the stacked-gate buffer (30) has a substrate (65) and a top substrate region (70) both with the same first conductivity type. The buffer (30) also has two transistors (95.105), each with a current carrying electrode and a control electrode (90, 100). A deep doped region (120) lies between the first (90) and second (100) control electrodes where the deep doped region (120) is another current carrying electrode for the first transistor (95) and another current carrying electrode for the second transistor (105) and the deep doped region (120) has a second conductivity that is opposite the first conductivity type. A deeper doped region (80) is also part of the stacked-gate buffer which has a second conductivity type and lies between the first (90) and second (100) control electrodes and is deeper than the deep doped region (120). A method of forming the device is also provided herein.

Abstract: The present invention is directed to fabricating a MOSFET-controlled FEA, in which the emitter array and the cathode electrode are separated and connected to each other by a MOSFET, the cathode electrode and the n-well beneath the emitter array thereby being used as a source and a drain of the MOSFET.

Abstract: A method for forming a borderless, contact or via hole, has been developed, in which a thin silicon nitride layer is used as an etch stop to prevent attack of an underlying interlevel dielectric layer, during the opening of the borderless, contact or via hole, in an overlying, interlevel dielectric layer. The thin silicon nitride layer is the top layer of an interlevel dielectric composite layer, used between metal interconnect levels.

Abstract: A chip scale package comprised of a semiconductor die having a silicon blank laminated to its active surface. The bond pads of the die are accessed through apertures micromachined through the blank. The package may be employed with wire bonds, or solder or other conductive bumps may be placed in the blank apertures for flip-chip applications. Further, the package may be employed to reroute external connections of the die to other locations, such as a centralized ball grid array or in an edge-connect arrangement for direct or discrete die connect (DDC) to a carrier. It is preferred that the chip scale package be formed at the wafer level, as one of a multitude of packages so formed with a wafer-level blank, and that the entire wafer be burned-in and tested to identify the known good die (KGD) before the wafer laminate is separated into individual packages.

Abstract: A method and apparatus for depositing a low dielectric constant film by reaction of an organo silane compound and an oxidizing gas at a low RF power level from 20-200 W. The oxidized organo silane film has excellent barrier properties for use as a liner or cap layer adjacent other dielectric layers. The oxidized organo silane film can also be used as an etch stop or an intermetal dielectric layer for fabricating dual damascene structures. The oxidized organo silane films also provide excellent adhesion between different dielectric layers. A preferred oxidized organo silane film is produced by reaction of methyl silane, CH.sub.3 SiH.sub.3, and nitrous oxide, N.sub.2 O, at a pulsed RF power level from 50-200 W during 10-30% of the duty cycle.

Abstract: A memory cell is provided. The memory cell includes a field-effect transistor having a source region, a drain region and a gate coupled to a wordline. The memory cell also includes a vertical bipolar junction transistor that is biased for use of the reverse base current effect to store data. The bipolar junction transistor has an emitter region formed within a source/drain region of the field-effect transistor. The emitter region is self-aligned with a minimum dimension isolation region adjacent to the memory cell and is coupled to a ground line. A portion of the source/drain region acts as the base of the bipolar junction transistor.

Abstract: An integrated circuit fabrication process is provided for forming a transistor having an ultra short channel length. First and second masks are formed upon a conductive gate layer, wherein the second mask has a second lateral dimension less than a first lateral dimension of the first mask. The second mask is used to pattern a gate conductor from the conductive gate layer such that the gate conductor has an ultra narrow lateral dimension. Lightly doped drain impurity areas are formed self-aligned to sidewall surfaces of the gate conductor. Spacers are formed laterally adjacent the sidewall surfaces of the gate conductor, and source and drain impurity areas are formed self-aligned to sidewall surfaces of the spacers.

Abstract: An interconnect in a microelectronic device is formed by forming a first mesa on a substrate. A first insulation layer is then formed on the substrate, the first insulation layer covering the first mesa to define a step at an edge thereof. A second mesa is formed on the first insulation layer adjacent the step, the second mesa being lower than the step. A second insulation layer is formed on the substrate, covering the second mesa and forming a step in the second insulation layer overlying the step in the first insulation layer. A spun-on-glass (SOG) layer on the second insulation layer, and then is planarized to expose a first portion of the second insulation layer at the step in the second insulation layer and to expose a second portion of the second insulation layer overlying the second mesa, thereby defining a planarized SOG region between the step and the second mesa.

Abstract: An integrated circuit (IC) package includes a mold compound, a die, and a window. The mold compound has a frame embedded within it. The frame has a coefficient of thermal expansion that is less than the mold compound. The IC package is capable of being attached to a circuit board via a mass reflow process.

Abstract: A micromachined multi-layered microbellows-style actuator capable of delivering larger deflections compared to a single layered flat membrane of comparable size. Anchor structures are disclosed that improve the strength of the microbellows membrane. A characterization apparatus is used to measure microbellows membrane performance. Thermopneumatic actuators having a resistive heater chip are also disclosed.

Abstract: A semiconductor flash memory device includes floating gate type field effect transistors serving as memory cells, field effect transistors for forming peripheral circuits and bipolar transistors for forming other peripheral circuits expected to drive heavy load at high speed, and both of the floating gate electrodes and the emitter electrodes and both of the control gate electrodes and the gate electrodes are patterned from a first doped polysilicon and a second doped polysilicon so as to simplify a process sequence for fabricating the semiconductor flash memory device.

Abstract: A wiring patterned film wherein a gold lead 18 which extends from a wiring pattern formed on the adhesive side of a resin film adhered to the side of a semiconductor element on which an electrode terminal is formed, and which bridges a window section opening on the resin film, is cut off at a prescribed location facing the window section and bent so that the lead tip is connected to the electrode terminal, wherein a notch section is formed at a prescribed location of the gold lead 18 bridging the window section to facilitate cutting of the gold lead 18, and at least the narrowest part of the notch section 42a is formed into an upward protruding convex curve at the surface opposite the back side facing the window section.

Abstract: A photo diode and a signal processing circuit are formed on a silicon substrate. The signal processing circuit comprises a PNP transistor and an NPN transistor. A region of the signal processing circuit on the silicon substrate is covered by an aluminum thin film functioning as a shielding film. A covered distance L(.mu.m) is defined as an overhang of the aluminum thin film from the edge of the PNP transistor, and is determined based on a ratio of a minimum current of the PNP transistor, which induces malfunction in the signal processing circuit under the solar radiation, to a current generated in the circuit element when subjected to the solar radiation without the aluminum thin film.

Abstract: A structure for a microwave device in which the minimum noise figure is reduced in that underneath the base terminal surface of a transistor, a highly-doped trenched layer is formed, which layer is connected to a reference potential in the vicinity of the base terminal surface via a standard collector contact.

Abstract: A semiconductor device having a multi-level interconnection structure is disclosed which includes a metal interconnect wire (2) formed on a surface of an interlayer dielectric film (7) serving as a base; a high-stress TEOS oxide film (5), an SOG film (3), and a low-stress TEOS oxide film (6) which are deposited as interlayer dielectric films; and a contact hole (4), thereby decreasing stresses applied from the interlayer dielectric films to the metal interconnect wire to prevent metal hillocks in the contact hole.

Abstract: A low-voltage high-current discrete insulated-gate field-effect transistor which is made by a very economical process with two silicon etches. A buried poly gate gates conduction along a trench sidewall. The channel is provided by the residuum of an epi layer, and the source diffusion is provided by an unmasked implant which is screened only by various grown oxides.

Abstract: A sapphire substrate, a buffer layer of undoped GaN and a compound semiconductor crystal layer successively formed on the sapphire substrate together form a substrate of a light emitting diode. A first cladding layer of n-type GaN, an active layer of undoped In.sub.0.2 Ga.sub.0.8 N and a second cladding layer successively formed on the compound semiconductor crystal layer together form a device structure of the light emitting diode. On the second cladding layer, a p-type electrode is formed, and on the first cladding layer, an n-type electrode is formed. In a part of the sapphire substrate opposing the p-type electrode, a recess having a trapezoidal section is formed, so that the thickness of an upper portion of the sapphire substrate above the recess can be substantially equal to or smaller than the thickness of the compound semiconductor crystal layer.

Abstract: An integrated circuit arrangement contains an MOS transistor surrounded by an insulation structure, the source and drain thereof being arranged laterally and in different depths. A channel thereof proceeds essentially perpendicular to the surface of the circuit arrangement. Since the channel length is determined by etching or by growing a layer, channel lengths as short as less than 50 nm can be realized. For the manufacture, most of the masks of the traditional circuit arrangements in which planar transistors are integrated are employed, this significantly facilitating incorporation into the semiconductor manufacture.

Abstract: A low-concentration impurity region and a high-concentration impurity region are formed respectively near the lower surface and the upper surface of an undoped polysilicon film by a first and second ion-implanations. A refractory metal film of tungsten or the like is formed on the polysilicon film. The impurities are thermally diffused to form shallow-junctions of source/drain having low-concentration impurities. Lead-out electrodes having a high-impurity concentration can be formed without impeding formation of the source and drain. The refractory metal film is converted into a silicide with the resistance at the interface between the polysilicon film and the silicide kept lowered.