Abstract: A semiconductor device having a gate electrode with a sidewall air gap is provided. In accordance with this embodiment, at least one gate electrode is formed over a substrate. A spacer is then formed adjacent an upper sidewall portion of the gate electrode such that an open area is left beneath the spacer. Next, a dielectric layer is formed over the spacer and the gate electrode, thereby leaving an air gap in the open area. In accordance with one aspect of the invention, both the gate electrode and the spacer adjacent the gate electrode are formed from polysilicon. This, for example, allows the formation of a wider contact area to the gate electrode.

Abstract: A polysilicon gate layer, a first n.sup.+ diffusion region serving as a drain region, and a second n.sup.+ diffusion region serving as a source region form a MOSFET, and then an operating point of the MOSFET is set into its saturation region by connecting a gate layer and a drain region of the MOSFET. The first and second n.sup.+ diffusion regions provide a first and a second leakage paths, respectively. A temperature sensor can be provided by use of the event that a leakage current flowing through the second leakage path is varied according to a substrate temperature. According to such configuration, scatter of detected temperatures due to scattering in manufacturing process can be reduced even if all scattering parameters in manufacturing process are considered. In addition, an required area of the temperature sensor can be made smaller since a high resistance value is not needed.

Abstract: A process for forming a semiconductor device having an elevated active region is disclosed. The process includes forming a plurality of gate electrodes on the semiconductor substrate and disposing a thick oxide layer over the gate electrodes. A trench is formed in a thick oxide layer and is filled with a polysilicon material. The polysilicon material is subsequently doped in order to form an elevated active region above an active region of the substrate.

Abstract: Integrated circuitry and a method of forming a contact landing pad are described. The method includes, in one embodiment, providing a substrate having a plurality of components which are disposed in spaced relation to one another; forming a silicon plug spanning between two adjacent components; forming a refractory metal layer over the silicon plug and at least one of the components; reacting the silicon plug and the refractory metal layer to form a silicide layer on the silicon plug; and after forming the silicide layer removing unreacted refractory metal layer material from the substrate.

Abstract: A semiconductor memory device includes an array of storage cells, each cell having a transfer transistor with a gate electrode. A separate wordline 32 interconnects the gate electrodes of each row of the storage cells. A first conductive layer includes stripes 38, each stripe overlying a different row of the storage cells and connecting to the wordline and the gate electrodes of the storage cells of a different odd numbered row of the storage cells. An insulator surrounds the stripes of the first conductive layer. A second conductive layer, separated from the stripes of the first conductive layer by the insulator, includes stripes 39, each stripe of the second conductive layer overlying a different even numbered row of storage cells and connecting to the wordline and the gate electrodes of the different even numbered row of storage cells.

Abstract: A method of forming an integrated circuit device, and in particular a CMOS integrated circuit device, having an improved lightly doped drain region. The methods include the steps of providing a semiconductor substrate with a P type well region and an N type well region. Gate electrodes are formed overlying gate dielectric over each P type well and N type well regions. The present LDD fabrication methods then provide a relatively consistent and easy method to fabricate CMOS LDD regions with N type and P type implants at a combination of different dosages and angles using first and second sidewall spacers, with less masking steps and improved device performance.

Abstract: A high density integrated circuit structure and method of making the same includes providing a first silicon substrate structure having semiconductor device formations in accordance with a first circuit implementation and metal interlevel lines disposed on a top surface thereof and a second silicon substrate structure having a second circuit implementation and metal interlevel lines disposed on a top surface thereof. The first substrate structure includes a planarized low-K dielectric disposed between the metal interlevel lines and a protective coating separating the metal interlevel lines from the low-K dielectric, the metal interlevel lines of the first silicon substrate structure have a melting temperature on the order of less than 500.degree. C. and the low-K dielectric having a dielectric K-value in the range of 2.0-3.8.

Abstract: A structure and method for forming a metal oxide semiconductor field effect transistor structure comprises, a substrate having a gate-channel region and source and drain regions adjacent the gate-channel region, a gate insulator over the substrate, a central gate conductor positioned above the gate-channel region and over the gate insulator and outer gate conductors over the gate insulator and adjacent the central gate conductor, wherein the gate insulator has a first thickness under the central gate conductor and a second thickness greater than the first thickness under the outer gate conductors. The center and outer gate conductors may consist of different material types (i.e., different work functions). The polarity of the source-drain doping is independent of the polarity of the central or outer gate conductors.

Abstract: The electronic device has a structure that a semiconductor package is mounted on a mother board. To relieve stress caused by cyclic thermal load and applied to solder bumps that are electrically and mechanically connect the semiconductor package and the mother board, a shape-holding plate (stiffener) adhered to a wiring film is composed of a metal with a thermal expansion coefficient of 13.times.10.sup.-6 to 17.times.10.sup.-6 almost close to that of a glass-epoxy wiring substrate as the mother board. Examples of the metal are 25Cr-20Ni stainless steel or copper alloy containing 0.01 to 0.03% by weight of Zr.

Abstract: The invention relates to a charge-coupled device. Such devices comprise at least one insulated conducting gate (3) connecting two semiconductor zones. According to the invention, each insulated conducting gate (3) has a width progressively increasing from the first semiconductor zone (1) to the second semiconductor zone (2). The width of each gate (3) is sufficiently narrow for the potential well created by the application of a voltage V to the gate to have a depth increasing progressively from the first zone (1) to the second zone (2), thus enabling the charges to be driven away. The invention applies to any type of charge-coupled device and particularly to photodiodes.

Abstract: A semiconductor package in which a semiconductor chip 16 is formed above a die pad 12 interposing a capacitor 22 therebetween, or the semiconductor chip 16 and the capacitor 22 in a vortex-shaped form are respectively formed on both faces of the die pad 12, or the condensers 22 are formed on both faces of the die pad 12 and the semiconductor chip 16 is formed on one of the condensers 22, and the die pad 12, the semiconductor chip 16 and the condensers 22 are sealed by resin by which adverse effect of noise is reduced, wherein the shape of the capacitor may be in a vortex-shaped form or opposed faces of metal layers may be roughened.

Abstract: Disclosed is a transistor structure having a semiconductor substrate with a active region and a field region, a recess region being defined by either the field region or the active region, a gate electrode formed on portions of the active and recess region, and impurity regions formed in the active region of the semiconductor substrate on either side of the gate electrode. The transistor structure has an active region with at least one groove formed therein, and the transistor structure being formed for a low voltage operation.

Abstract: A process is provided for forming dielectric structures having a relatively low dielectric constant arranged adjacent to the opposed lateral edges of a trench isolation structure. In an embodiment, an opening is etched vertically through a masking layer arranged upon a semiconductor substrate, thereby exposing the surface of the substrate. A patterned photoresist layer is formed upon the masking layer using optical lithography to define the region to be etched. Sidewall spacers made of a low K dielectric material are formed upon the opposed sidewall surfaces of the masking layer within the opening. The sidewall spacers are formed by CVD depositing a dielectric material within the opening and anisotropically etching the dielectric material until only a pre-defined thickness of the material remains upon the masking layer sidewall surfaces. Thereafter, a trench defined between the exposed lateral edges of the sidewall spacers is formed within the substrate.

Abstract: A single polysilicon DRAM cell is disclosed. The DRAM cell comprises: a deep n-well in a silicon substrate; a p-well within the deep n-well; a gate structure over and straddling the deep n-well and the p-well, the gate structure being a stack of a thin gate oxide layer and a conductive layer; and a n+ well within the p-well and adjacent to a sidewall of the gate structure. The p-well potential can be reset to -V.sub.cc /2 representing "0", and written to V.sub.cc /2 representing "1". The parasitic n-channel MOS with the p-well as the "body" will have a threshold voltage modulated by the p-well potential at V.sub.cc /2 and -V.sub.cc /2 for representing "1" and "0" states, respectively.

Abstract: The present invention discloses an integrated circuit that is wired with a high-temperature superconductive material that is superconductive at temperatures of about 70.degree. K and above, and methods of making the integrated circuit. The front-end manufactured semiconductor structure is patterned with a preferred precursor metal or metal oxide and a complementary compound is superposed and reacted to form wiring lines of superconductor ceramics that complete integrated circuits within the front-end manufactured semiconductor structure. The front-end manufactured semiconductor structure is alternatively patterned first with the complementary compound and the precursor metal is thinly patterned by ion implantation. The front-end manufactured semiconductor structure is then treated to form wiring lines of superconductor ceramics that complete integrated circuits within structure.

Abstract: Apparatus for retaining a semiconductor wafer in a semiconductor wafer processing system. The apparatus comprises a support pedestal for supporting the wafer, first and second coplanar electrodes in the support pedestal for creating a chucking force, a cathode electrode for establishing wafer processing conditions and a third gap fill electrode positioned vertically between the first and second electrodes, such that the gap fill electrode is radially coincident with the gap between the first and second electrodes. A method of making the wafer retaining apparatus may comprise the steps of depositing electrode layers over molten, drawn sapphire layers to form a unitary bipolar electrostatic chuck having a gap fill electrode spaced between a pair of bipolar chucking electrodes and an RF powered electrode and radially coincident with the gap between the bipolar chucking electrodes.

Abstract: An integrated circuit device interconnect with controlled inductance. An integrated circuit device includes an insulating layer formed on a substrate and a an interconnect disposed on the insulating layer extending along a first path. A dedicated current return path having one end configured to be coupled to ground is disposed on the first insulating layer parallel to the interconnect, such that the signal received by the interconnect is returned to ground via the dedicated current return path when the dedicated current return path is coupled to ground. Inductance of the interconnect is thus controlled by reducing the area of the circuit loop formed by the interconnect and the parallel dedicated current return path. In one embodiment, the dedicated current return path is formed in an embedded ground plane just above or below the first interconnect.

Abstract: A power MOSFET suitable for use in RF applications and a method for making the same is disclosed. The power MOSFET reduces the gate coverage of the drain region of the device in order to decrease the device gate to drain capacitance C.sub.gd. A significant portion of the gate overlaying the drain region is eliminated by the removal of a portion of a polysilicon layer that is disposed over a substantial portion of the drain region that resides between the channel portions of the body regions of the device. The resulting open area, that is subsequently covered by an oxide layer, separates the polysilicon gate electrodes of the device. Finally, a metal layer is deposited over the entire structure to form the gate and source electrodes of the device.

Abstract: A superconductor-normal conductor junction device comprises first and second regions (1, 3) of normal material forming first and second junctions with a superconducting material (2), the Fermi level of the first region of normal material being so arranged relative to a given energy level in the superconducting material that charge carriers in the first normal material undergo Andreev reflection at the first junction, resulting in pairs of the charge carriers entering said given energy level in the superconducting material, and the Fermi level of the second region of normal material being so arranged relative to said given level in the superconducting material that said charge carriers conduct from the superconducting material through the second region.

Abstract: A multi-chip stack package does not include a die pad. The elimination of the die pad provides more room for elements in the package which. Thus, a balanced inner package structure can be achieved, and a poor molding which may expose one of the package elements can be avoided. In the package, an upper chip is bonded to the top surface of a lower chip. To stabilize the chips, auxiliary or inner leads of a lead frame attach to the top surface of a lower chip. This shortens wire lengths between the chips and the inner leads. The shorter wires reduce wire loop heights and thus reduce the probability of exposing wires in a subsequent transfer-molding. A multi-chip stack package which includes an auxiliary lead(s) is also disclosed. The auxiliary leads attach to the top surface of the lower chip and can provide a stable support of a semiconductor chip and prevent the chip from tilting and shifting in transfer-molding. An auxiliary lead can be between the lower and upper chips.