Abstract: The present invention includes a normal NMOS device region and a NMOS cell region for coding. An isolation structure is formed between the normal NMOS device region and the NMOS cell region. A gate oxide is formed on the normal NMOS device region and a coding oxide is formed on the NMOS cell region. A polysilicon layer is formed on the gate oxide. Gates are respectively formed on the polysilicon layer and the coding oxide. Spacers are formed on the side walls of the gates. LDD structures are formed under the spacers and adjacent to the gates. Source and drain regions are formed next to the LDD structures. A p type conductive region is formed adjacent to the surface of the NMOS cell region and under the coding oxide.

Abstract: A lead frame includes a conductive base plate having a first surface on which a semiconductor element is to be mounted and a second surface opposite to the first surface, a lead forming portion arranged on the first surface of the conductive base plate, in a concavity in the first surface through etching by masking at least the lead forming portion. The lead forming portions are coupled with one another, and are not independent. Thus, bending of the lead forming portion in a lead frame is avoided. A semiconductor device using the lead frame, and methods for manufacturing the lead frame are also disclosed.

Abstract: Obtained is a semiconductor light emitting device in which a light emitting device chip is bonded on a first lead and a second lead is electrically connected to one electrode of the light emitting device chip. Besides, the light emitting device chip and the top end of the second lead are enclosed by resin which a light from the light emitting device chip transmits. The first and second leads are respectively enclosed by heat resistant enclosing material along predetermined lengths of both leads at the bottom of the package, which is opposed to the light emitting surface. As a result, adhesiveness between the resin package and the leads is improved and thereby prevented is corrosion of the leads and the light emitting device chip in the package from occurring, which can make reliability improved.

Abstract: Compounds of the general formula A.sub.4 MeSb.sub.3 O.sub.12 wherein A is either barium (Ba) or strontium (Sr) and Me is an alkali metal ion selected from the group consisting of lithium (Li), sodium (Na) and potassium (K) have been prepared and included in high critical temperature thin film superconductors, ferroelectrics, pyroelectrics, piezoelectrics, and hybrid device structures.

Abstract: The present invention proposes a novel structure of nonvolatile memories with recessed floating gates. A plurality of field oxides is formed on a semiconductor substrate. Buried bit lines are formed in the semiconductor substrate and beneath the field oxides. Between the field oxides over the buried bit lines, trenched floating gates are formed in the semiconductor substrate. Tunnel dielectrics are formed between the trenched floating gates and the semiconductor substrate. The interpoly dielectric is formed over the field oxides and the trenched floating gates and the control gates are formed on the interpoly dielectric. Because of the large area of the recessed tunnel dielectric and the recessed length of the channel, high-density shallow trench contactless nonvolatile memories can be achieved.

Abstract: A semiconductor device assembly having a support such as a lead frame paddle comprises a coating thereon to reduce or eliminate the flow of die attach adhesive from under the die and over bond sites or encapsulation regions. Thus undesirable effects resulting from this flow of adhesive, such as wire bonding problems and encapsulation problems, are reduced. A method for forming the assembly is also described.

Abstract: An integrated device comprises a high-voltage transistor and a low-voltage transistor in an emitter-switching configuration integrated in a chip (400) of semiconductor material comprising a buried P-type region (120) and a corresponding P-type contact region (405) which delimit a portion of semiconductor material within which the low-voltage transistor is formed. The contact region (405) has a network structure such as to divide this portion of semiconductor material into a plurality of cells (410) within each of which there is an elemental P-type base region (425) and an elemental N-type emitter region (430) of the low-voltage transistor. The elemental regions (425) and (430) of the various cells (410) are electrically connected to one another by means of surface metal contacts.

Abstract: A method for providing pre-placed, pre-brazed feed throughs in the substrate of a hermetic package corresponding to the terminal leads of the encased circuit COTS components. The substrate may include directly bonded copper (DBC) regions forming circular shapes where the holes for the special connectors of the present invention will be located. These holes will correspond to the leads of the COTS component that will be mounted to it. Holes are laser or mechanically drilled into the substrate inside the circular shapes formed in the DBC. To form the feed through, a bushing, such as a blind copper rivet, is brazed in the hole, with the open end thereof oriented toward the component-side of the substrate. These open ends can accept the leads of the COTS component, like the holes of a conventional PC circuit board.

Abstract: Planar magnetic motor (100), characterized by the fact that it comprises a plurality of magnetic poles (111, 121) made of a ferromagnetic material placed at the center of planar coils (110, 120) constituted by at least one layer of turns produced on the surface of a substrate (150) made of a ferromagnetic material, the turns being wound and connected to each other so as to combine the magnetic fluxes generated by the magnetic poles (111, 121). The invention can be used to produced magnetic motors and microactuators.

Abstract: A transistor having a source/drain metal silicide in close proximity to the channel region may be formed according to the following process. A masking structure is formed upon a semiconductor substrate, and a metal is deposited self-aligned to sidewall surfaces of the masking structure. The metal is then annealed to form a metal silicide. Following formation of lightly doped drain impurity areas self-aligned to the sidewall surfaces of the masking structure, spacers may be formed adjacent the sidewall surfaces and source and drain impurity areas may be formed self-aligned to sidewall surfaces of the spacers. Fill structures are then formed adjacent the spacers and the masking structure is removed to form an opening between the spacers. A gate dielectric is formed upon the exposed upper surface of the semiconductor substrate within the opening, and a gate conductor is formed within the opening.

Abstract: An electromagnetic-wave detector having an electromagnetic-wave detection unit having the structure that M (M.gtoreq.1) contiguous pairs of a metallic layer and an insulating layer are provided at the side of incidence of an electromagnetic-wave, such as X-rays.

Abstract: A gate insulating film and gate electrodes are formed on a substrate containing N-type impurities such as P or As. Under the gate insulating film is a gate region on both sides of which are a first and a second source drain region. The gate region is furnished in its central part with a high-concentration channel injection region containing N-type impurities at a concentration higher than that of the substrate. Between the high-concentration channel injection region on the one hand and the first and the second source drain region and on the other hand, there are formed a first and a second low-concentration channel injection region and having substantially the same impurity concentration as that of the substrate.

Abstract: A self-biased solar cell and a module adopting the solar cell. The self-biased solar cell includes a semiconductor substrate of first conductivity type, a semiconductor layer of second conductivity type disposed adjacent to the first surface of the semiconductor substrate, at least one more first electrodes formed adjacent to the semiconductor layer; at least one more dielectric layers formed on the second surface of the semiconductor substrate, at least one or more second electodes formed on the second surface of the semiconductor substrate, the second electodes being disposed adjacent to the dielectric layers, and at least one or more voltage applying electrode formed on the dielectric layers. Therefore, recombination loss of the carriers according to the formation of a back surface field is comparatively decreased, and open voltage and quantum efficiency at a long wavelength are increased.

Abstract: An electronic component includes a substrate (301, 801), a leadframe (101, 601, 710) coupled to a first surface of the substrate (301, 801) and extending beyond the first surface and towards a second surface of the substrate (301, 801), and an electrically conductive layer coupled to the second surface and coplanar with a contact portion of the leadframe (101, 601, 710) where the leadframe (101, 601, 710) and the electrically conductive layer form a package around the substrate (301, 801).

Abstract: The object of the present invention is to provide a semiconductor chip package structure in which thermal stress exerted on a wiring substrate is mitigated to improve the reliability of the bond between the semiconductor chip and the wiring substrate and the bond between the wiring substrate and the motherboard.To achieve the above object, the present invention provides a semiconductor chip package structure in which a semiconductor chip is mounted on a wiring substrate by flip chip bonding to a wiring pattern on the wiring substrate, comprising: a large number of electrode terminals disposed on an electrode arrangement surface of the semiconductor chip; a first group of the electrode terminals electrically connected to the wiring pattern by an adhesive layer; and a second group of the electrode terminals electrically connected to the wiring pattern by an elastomer layer.

Abstract: A bidirectional horizontal charge transfer device and method includes a charge transfer area formed within a substrate, a plurality of first, second, third and fourth poly gates formed over the charge transfer area,an insulating layer formed between the first, second, third and fourth poly gates, a first clock signal applied to the first and second poly gates, a second clock signal applied to the third and fourth poly gates, and a biasing circuit for selectively applying a bias signal to the first and second clock signals so as to selectively change a charge transfer direction.

Abstract: The formation of routing traces on an external surface of a semiconductor device, such as a flip-chip, which has a plurality of ball or bump sites patterned in specific locations, wherein the ball or bump sites are in electrical communication with external communication traces which are used to route signals from the flip-chip integrated circuitry. Such external communication traces generally result in unused space on the exterior surface of the flip-chip. This unused space can be utilized for forming routing traces to connect portions of the internal circuitry of the flip-chip rather than forming such routing traces internally, for forming routing traces to connect two or more semiconductor dice, or for forming routing traces for use as repair mechanisms.

Abstract: A MOSFET includes a semiconductor substrate of a first conductivity type including a field region and an active region; a gate insulating film on a portion of the active region, the gate insulating film having two edge parts and a mid-part, the two edge parts being thicker than the mid-part; a gate electrode on the gate insulating film; sidewall spacers on the sides of the gate electrode and the gate insulating film; heavily doped regions of a second conductivity type in the semiconductor substrate under the two edge parts of the gate insulating film; normally doped regions of the second conductivity type in the semiconductor substrate on both sides of the gate insulating film; lightly doped regions of the second conductivity type in the semiconductor substrate on the sides of the sidewall spacers; and doped regions of the first conductivity type below the normally doped region of the second conductivity type under the sidewall spacers.

Abstract: A semiconductor package includes a base plate, a semiconductor die having top and bottom surfaces, the bottom surface being mounted to the base plate, and a conductor tab having first and second ends, the first end being adapted to communicate with and couple to external circuitry, the second end including a relatively wide foot having a plurality of finger portions separated by gaps, the finger portions being mounted to an covering a substantial portion of the top surface of the semiconductor die.

Abstract: A multi-level metal interconnect structure in a semiconductor device includes a plurality of overlying metal layers separated by ILD layers and electrically connected by filled vias in the ILD layers. Each metal layer includes a relatively thick antireflective layer for improved electromigration resistance. Each metal layer also includes a metal lining layer and a metal interconnect layer overlying the metal lining layer. Enhanced electromigration resistance is obtained by forming the antireflective layer to a thickness of no less than the thickness of the metal lining layer. In a preferred embodiment of the invention, the antireflective layer has a thickness of about 1000 angstroms.