Abstract: A thin film transistor array includes thin film transistors positioned in a matrix, each of the thin film transistors including a substrate, a gate electrode formed on the substrate, a gate insulation layer formed on the gate electrode, a source electrode formed on the gate insulation layer, a drain electrode formed on the gate insulation layer, a pixel electrode formed on the gate insulation layer and connected to the source electrode and the drain electrode, a semiconductor layer formed between the source electrode and the drain electrode, an interlayer insulation film covering the source electrode, the drain electrode, the semiconductor layer and a portion of the pixel electrode, and an upper pixel electrode formed on the interlayer insulation film and connected to the pixel electrode. The interlayer insulation film has one or more concave portions and one or more via hole portions.

Abstract: A light emitting device includes a base member including a conductive member containing silver. A light emitting element has an upper surface below an upper surface of a side wall portion. A wire electrically connects the light emitting element and the conductive member. A protective film covers the conductive member to be spaced apart from at least a part of at least one connecting portion connecting the wire and the conductive member. A first resin member continuously covers at least a portion of each of the protective film, a portion of the conductive member around the connecting portion, and the wire. The first resin member has a first gas barrier property with respect to hydrogen sulfide. A second resin member covers the light emitting element and the first resin member and has a second gas barrier property with respect to hydrogen sulfide lower than the first gas barrier property.

Abstract: Disclosed are a heterocyclic compound and an organic light emitting device including the same.

Abstract: Provided are a laminate including an organic material mask and a method for preparing an organic light emitting device using the same. The laminate includes a substrate; and a mask provided on the substrate and including an organic material.

Abstract: A QD glass cell includes a glass cell and QD fluorescent powder material. The glass cell includes a receiving chamber, and the QD fluorescent powder being encapsulated within the receiving chamber. A manufacturing method of the QD glass cell includes: S101: manufacturing a glass cell comprising a receiving chamber, and the glass cell comprising an injection port transmitting fluid into the receiving chamber; S102: manufacturing fluid QD fluorescent powder material; S103: filling the fluid QD fluorescent powder material into the receiving chamber via the injection port; S104: applying a curing process to the fluid QD fluorescent powder material within the receiving chamber; and S105: sealing the injection port by hot melting to obtain the QD glass cell. In addition, the above QD glass cell may be applied to LED light source.

Abstract: At least one method, apparatus and system are disclosed for forming a fin field effect transistor (finFET) while reducing oxidization and fin critical dimension loss. A plurality of fins of a transistor are formed. A hard mask layer is formed on top of the fins. A first liner layer is formed over the fins and the hard mask layer. A partial deposition process is performed for depositing a first insulation material in a first portion of a channel between the fins. A second liner layer is formed above the fins, the first insulation material, and the channel. A second insulation material is deposited above the second liner layer. A fin reveal process is performed for removing the second insulation material to a predetermined height. An etch process is performed for removing the hard mask layer and the first and second liner layers above the predetermined height.

Abstract: Atomic layer deposition in selected zones of a workpiece surface is accomplished by transforming the surfaces outside the selected zones to a hydrophobic state while the materials in the selected zones remain hydrophilic.

Abstract: An OLED device and a fabrication method thereof, a display substrate and a display device are provided. The OLED device comprises: a base substrate, and an anode, an organic light emitting layer and a cathode which are sequentially stacked on the base substrate. The anode includes a silver nanowire material.

Abstract: Resistance increase in Cobalt interconnects due to nitridation occurring during removal of surface oxide from Cobalt interconnects and deposition of Nitrogen-containing film on Cobalt interconnects is solved by a Hydrogen thermal anneal or plasma treatment. Removal of the Nitrogen is through a thin overlying layer which may be a dielectric barrier layer or an etch stop layer.

Abstract: A semiconductor device is manufactured in a semiconductor body by forming an initial mask on a process surface of a semiconductor layer, openings in the mask exposing a part of the semiconductor layer in alignment structure and super-junction structure areas. A recess structure is formed in the semiconductor layer at portions of the process surface that are exposed by the openings, the recess structure in the alignment structure area constituting an initial alignment structure. Dopants are introduced into the semiconductor layer through portions of the process surface that are exposed by the openings of the initial mask. The dopants introduced in the super-junction area constitute part of a super-junction structure. A thickness of the semiconductor layer is increased by growing an epitaxial layer. The initial alignment structure is imaged into the process surface. Dopants are introduced into the semiconductor layer by using a mask aligned to the initial alignment structure.

Abstract: The present disclosure is directed to a method that includes exposing a surface of a silicon substrate in a first region between first and second isolation trenches, etching the silicon substrate in the first region to form a recess between the first and second isolation trenches, and forming a base of a heterojunction bipolar transistor by selective epitaxial growth of a film comprising SiGe in the recess.

Abstract: A method for manufacturing an array substrate includes coating a photoresist onto an insulation layer including a gate insulation layer and an etch stop layer, wherein the gate insulation layer covers a conductive pattern and the etch stop layer covers a semiconductive pattern. The method further includes exposing the photoresist to form a photoresist partially-reserved region and a photoresist unreserved region. The method further includes performing a first etching process to at least partially remove a portion of the insulation layer located at a position corresponding to the photoresist unreserved region, to form an intermediate hole. The method further includes performing a second etching process to form the first via hole and form the second via hole at a position of the intermediate hole, thereby to reveal the semiconductive pattern and the conductive pattern at positions corresponding to the first via hole and the second via hole, respectively.

Abstract: A method for producing optoelectronic semiconductor components and an optoelectronic semiconductor component are disclosed. In an embodiment the method includes: A) creating a blank by pultrusion from a glass melt, B) shaping the blank into a billet-shaped optical element with a longitudinal axis, the optical element having a mounting side and a light outlet side, C) producing conductor tracks on the mounting side, D) mounting a plurality of optoelectronic semiconductor chips on the mounting side of the optical element and connecting them to the conductor tracks and E) separating the optical element into the optoelectronic semiconductor components, wherein each optoelectronic semiconductor component comprises at least two of the semiconductor chips, and wherein at least steps A) to D) are performed in the stated sequence.

Abstract: An array substrate and a display panel. The array substrate includes an active region and a peripheral circuitry region surrounding the active region; a plurality of scan lines and a plurality of data lines intersected with and insulated from the scan lines; a plurality of pixel driving circuit units disposed at intersection areas between the scan lines and the data lines; a plurality of first electrodes respectively electrically connected to the plurality of pixel driving circuit units and disposed in the active region and the peripheral circuitry region of the array substrate; and a plurality of first connection lines configured to electrically connect the pixel driving circuit units to the corresponding first electrodes.

Abstract: A core substrate is prepared first, a bottom redistribution layer RDL1 is formed. Any warpage of the RDL1 is suppressed by the core substrate. In a later process, warpage is further suppressed by a molding compound encapsulating the core substrate. A plurality of metal pillars are formed passing through the core substrate longitudinally; a top redistribution layer RDL2 is then formed on a top surface of the metal pillars.

Abstract: A manufacturing method of a display substrate, including preparing a carrier substrate; preparing a mixture of an organic material, an inorganic particle, and solvent; coating the mixture on the carrier substrate; forming a sacrificial layer including the inorganic particle in the organic material by curing the mixture; forming a barrier layer on the sacrificial layer; forming a display substrate on the barrier layer; and separating the barrier layer and the display substrate from the carrier substrate by applying a laser to the sacrificial layer.

Abstract: Disclosed herein is a method of dividing rectangular plate-shaped workpieces into individual device chips including a detecting step wherein an annular frame to which a plurality of rectangular plate-shaped workpieces are stuck is held on a chuck table and the positions and angles of the projected dicing lines on each of the plate-shaped workpieces are detected, and a dividing step wherein a laser beam having a wavelength which is absorbable by the plate-shaped workpieces is applied from a laser beam applying unit to the plate-shaped workpieces while the chuck table and the laser beam applying unit are being relatively processing-fed and finely adjusted for each of the plate-shaped workpieces on the basis of the positions and angles detected in the detecting step, thereby dividing the plate-shaped workpieces into a plurality of device chips along the projected dicing lines.

Abstract: A semiconductor device manufacturing method includes forming a first film on a substrate having a first region and a second region. A second film is formed on the first film. Guide grooves are formed by removing portions of the second film and exposing the first film. A self-assembly material is coated on the exposed first film and heated to cause a phase separation into a first and a second phase section. The self-assembly material is irradiated. A mask pattern including at least a portion of the first phase section is formed by removing the second phase section. The mask pattern has a first dimension in the first region and a second dimension in the second region that is different from the first dimension. The first film is etched after the mask pattern is formed.

Abstract: A method of manufacturing a silicon carbide semiconductor device includes grinding a back surface of a semiconductor substrate formed of silicon carbide to reduce thickness thereof and provide an altered layer that is ground; removing by polishing or etching, the altered layer from the back surface; forming a nickel film on the back surface of the semiconductor substrate after removing the altered layer; heat treating the nickel film to forming a nickel silicide layer by silicidation; and forming a metal electrode on a surface of the nickel silicide layer.

Abstract: The present disclosure relates to a process for fabricating a plurality of semiconductor-on-insulator structures, the insulator being a layer of silicon dioxide having a thickness smaller than 50 nm, each structure comprising a semiconductor layer placed on the silicon dioxide layer, the fabrication process comprising a step of heat treating the plurality of structures, which heat treatment step is designed to partially dissolve the silicon dioxide layer, the heat treatment step being carried out in a non-oxidizing atmosphere and the pressure of the non-oxidizing atmosphere being lower than 0.1 bar.