Abstract: A TFT device of a liquid crystal display and a manufacturing method therefor are provided. The TFT device has: a substrate; a first metal layer formed on the substrate on which a first silicon nitride protective film is deposited; a second metal layer deposited on the first silicon nitride protective film on which a second silicon nitride protective film is deposited; and a conductive film deposited on the second metal layer where the second silicon nitride protective film is etched, and connected with the first metal layer through a contact hole which passes through the first and second silicon nitride protective films, so that the first and second metal layers are connected. Thus, the connecting distance of the conductive film between the different metal layers and the contact resistance between metals are decreased, so as to enhance the product yield rate and the competitive capability of the product.

Abstract: In order to form a fine mask pattern with high accuracy, in a mask blank in which a light-semitransmissive film, a light shielding film, and a hard mask film are laminated in the stated order on a transparent substrate, the light-semitransmissive film containing silicon and additionally nitrogen, the hard mask film containing silicon or tantalum, and additionally oxygen, the light shielding film having the laminate structure of a lower layer, an intermediate layer, and an upper layer and containing chromium, conditions on the light shielding film are adjusted so that etching rates using a mixture gas of chlorine and oxygen are the lowest for the upper layer and the next lowest for the lower layer.

Abstract: Presented herein is a package comprising a carrier device of a device stack and at least one top device of the device stack mounted on a first side of the carrier device. A lid is mounted on the first side of the carrier device, with a first portion of the lid attached to the carrier device and a second portion of the lid extending past and overhanging a respective edge of the carrier device. The lid comprises a recess disposed in a first side, and the at least one top device is disposed within the recess. A thermal interface material disposed on the top device and contacts a surface of the recess.

Abstract: An integrated circuit structure and formation thereof. The integrated circuit structure includes a substrate and a front-end-of-the-line (FEOL) portion. The FEOL portion rests on top of and in contact with the substrate. The integrated circuit structure includes a memory level portion. The memory level portion rests on top of and in contact with the FEOL portion. The integrated circuit structure includes a back-end-of-the-line (BEOL) portion. The BEOL portion rests on top of and in contact with the memory level portion. The integrated circuit structure includes a multiple layer that includes one or more pairs of reactive materials. The multiple layer is one or more of: i) on top of the BEOL portion; ii) within the BEOL portion; iii) within the memory level portion; iv) within the FEOL portion; v) embedded in the substrate; and vi) on bottom of a thinned substrate.

Abstract: A method for manufacturing fins includes following steps. A substrate including a plurality of fins formed thereon is provided. At least an ion implantation is performed to the fins. A thermal process is performed after the ion implantation. An insulating layer is formed on the substrate, and the fins are embedded in the insulating layer. Thereafter, a portion of the insulating layer is removed to form an isolation structure on the substrate, and the fins are exposed from a top surface of the isolation structure. The insulating layer is formed after the ion implantation and the thermal process. Or, the isolation structure is formed before the ion implantation, or between the ion implantation and the thermal process.

Abstract: An optoelectronic semiconductor device has a semiconductor body including a semiconductor layer sequence with an active region that generates radiation, a semiconductor layer and a further semiconductor layer, wherein the active region is arranged between the semiconductor layer and the further semiconductor layer, a current spreading layer is arranged on a radiation exit face of the semiconductor body, the current spreading layer connects electrically conductively with a contact structure for external electrical contacting of the semiconductor layer, in a plan view of the semiconductor device the current spreading layer adjoins the semiconductor layer in a connection region, and the current spreading layer includes a patterning with a plurality of recesses through which radiation exits the semiconductor device during operation.

Abstract: A large-caliber telescope non-linear interference detecting and filtering method is provided. The measure of the oil pad interference is accomplished with one of the following two methods, accelerometer and encoder, or using both of the said methods simultaneously. The filtering of the oil pad interference: set a NOTCH frequency as the main interfering frequency by using NOTCH filter to filter the interference and distinctly improve the telescope performance. The telescope and method is specific to a large-caliber telescope with an oil pad, by using an acceleration sensor and an encoder to precisely measure the non-linear interfering frequency of the telescope oil pad system, by using a NOTCH digital filter to accurately filter the interference due to the oil pad system, and through adjusting parameters of the digital filter to change the filter frequency band on the basis of the change of the oil pad interfering frequency.

Abstract: Method of making a transistor with semiconducting nanowires, including: making a semiconducting nanowire on a support, one portion of the nanowire being covered by a dummy gate, in which the dummy gate and the nanowire are surrounded by a dielectric layer, removing the dummy gate, forming a first space surrounded by first parts of the dielectric layer, making an ion implantation in a second part of the dielectric layer under said first portion, said first parts protecting third parts of the dielectric layer, etching said second part, forming a second space, making a gate in the spaces, and a dielectric portion on the gate and said first parts, making an ion implantation in fourth parts of the dielectric layer surrounding second portions of the nanowire, the dielectric portion protecting said first and third parts, etch said fourth parts.

Abstract: A semiconductor device including an oxide conductor with high conductivity and high transmittance is provided. A manufacturing method for a semiconductor device includes the steps of: forming an oxide semiconductor over a first insulator; forming a second insulator over the first insulator and the oxide semiconductor; forming a first conductor over the second insulator; forming an etching mask over the first conductor; forming a second conductor including a region overlapping with the oxide semiconductor by etching the first conductor with use of the etching mask as a mask; removing the etching mask; and performing heat treatment after forming a hydrogen-containing layer over the second insulator and the second conductor.

Abstract: An OLED backplate structure is provided. Multiple auxiliary conducting layers contacting a cathode of the OLED are provided under the cathode in order to diminish the electrical resistance of the cathode to thereby enhance the conductivity of the cathode and to even the in plane voltages. The uniformity of the OLED display can be improved to prevent the uneven brightness issue and to decrease the thickness of the cathode for saving the production cost.

Abstract: In accordance with the disclosed semiconductor chip and multi-chip module, signal transmission is made possible between semiconductor chips that are placed on a plane so as to be adjacent to each other through inductive coupling without affecting other coils such as in an oscillation circuit or an antenna circuit for RF communication. A multilayer solenoid coil, where a plane of the coil formed in a multilayer wiring structure in a semiconductor body is parallel to a main surface of the semiconductor body, is formed along at least one side end surface of the semiconductor body.

Abstract: A semiconductor integrated circuit is capable of being supplied with battery current information and battery voltage information. The semiconductor integrated circuit includes a memory function, a current integrating function, a voltage-based state of charge operating function, a current-based state of charge operating function, a comparison determination function, a correcting function, and a resistance deterioration coefficient output function. The memory function stores the relation between a state of charge of a battery and an internal resistance deterioration coefficient thereof. The full charge capacity outputted from the correcting function and the internal resistance deterioration coefficient outputted from the resistance deterioration coefficient output function are stored in the memory function when a voltage-based state of charge and a current-based state of charge compared by the comparison determination function are determined to substantially coincide with each other.

Abstract: A method of manufacturing a display device includes forming a display portion on a substrate, and forming an encapsulation portion for sealing the display portion. The forming of the encapsulation portion includes forming a first layer covering the display portion, forming a second layer on the first layer, and forming a third layer on the second layer. The first layer is formed by maintaining a distance between an upper surface of the display portion and a mask by a first interval. The second layer is formed by maintaining a distance between an upper surface of the first layer and the mask by a second interval that is different from the first interval. The third layer is formed by maintaining a distance between an upper surface of the second layer and the mask by a third interval that is different from the second interval.

Abstract: An electronic chip including: a plurality of first semiconductor bars of a first conductivity type and of second semiconductor bars of a second conductivity type arranged alternately and contiguously on a region of the first conductivity type; two detection contacts arranged at the ends of each second bar; a circuit for detecting the resistance between the detection contacts of each second bar; insulating trenches extending in the second bars down to a first depth between circuit elements; and insulating walls extending across the entire width of each second bar down to a second depth greater than the first depth.

Abstract: A method of manufacturing a thin-film transistor (TFT) substrate including a thin-film transistor having a CuMn alloy film. The method includes controlling a contact resistance of a surface of the CuMn alloy film on the basis of a contact angle of the surface of the CuMn alloy film.

Abstract: A QD glass cell includes a glass cell and QD fluorescent powder material. The glass cell includes a receiving chamber, and the QD fluorescent powder being encapsulated within the receiving chamber. A manufacturing method of the QD glass cell includes: S101: manufacturing a glass cell comprising a receiving chamber, and the glass cell comprising an injection port transmitting fluid into the receiving chamber; S102: manufacturing fluid QD fluorescent powder material; S103: filling the fluid QD fluorescent powder material into the receiving chamber via the injection port; S104: applying a curing process to the fluid QD fluorescent powder material within the receiving chamber; and S105: sealing the injection port by hot melting to obtain the QD glass cell. In addition, the above QD glass cell may be applied to LED light source.

Abstract: A number of first hard mask portions are formed on a dielectric layer to vertically shadow a respective one of a number of underlying gate structures. A number of second hard mask filaments are formed adjacent to each side surface of each first hard mask portion. A width of each second hard mask filament is set to define an active area contact-to-gate structure spacing. A first passage is etched between facing exposed side surfaces of a given pair of neighboring second hard mask filaments and through a depth of the semiconductor wafer to an active area. A second passage is etched through a given first hard mask portion and through a depth of the semiconductor wafer to a top surface of the underlying gate structure. An electrically conductive material is deposited within both the first and second passages to respectively form an active area contact and a gate contact.

Abstract: The present invention is a method of incorporating a non-volatile memory into a CMOS process that requires four or fewer masks and limited additional processing steps. The present invention is an epi-silicon or poly-silicon process sequence that is introduced into a standard CMOS process (i) after the MOS transistors' gate oxide is formed and the gate poly-silicon is deposited (thereby protecting the delicate surface areas of the MOS transistors) and (ii) before the salicided contacts to those MOS transistors are formed (thereby performing any newly introduced steps having an elevated temperature, such as any epi-silicon or poly-silicon deposition for the formation of diodes, prior to the formation of that salicide). A 4F.sup.2 memory array is achieved with a diode matrix wherein the diodes are formed in the vertical orientation.

Abstract: There is provides a method of fabricating a semiconductor device to decrease contact resistance of source/drain regions and gate electrodes and thereby improve operation performance. The method includes providing an exposed silicon region, forming a rare earth metal silicide film on the exposed silicon region, the rare earth metal silicide film contacting the silicon region, and forming a contact on the rare earth metal silicide film, the contact being electrically connected to the exposed silicon region, wherein the rare earth metal silicide film is formed by simultaneously supplying a rare earth metal and silicon to the exposed silicon region using physical vapor deposition.

Abstract: One illustrative method disclosed includes, among other things, forming a plurality of gates above a substrate, each of the gates comprising a gate structure and a first layer of a first insulating material positioned on an upper surface of the gate structure, and forming a second layer of a second insulating material above insulating material positioned above the substrate between the laterally spaced apart gates, wherein the first insulating material and the second insulating material are selectively etchable relative to one another. The method may also include selectively removing a portion of the first layer to thereby expose a portion of the gate structure of at least one of the gates, selectively removing the exposed portion of the gate structure so as to thereby define a gate-cut cavity, and forming an insulating gate-cut structure in the gate-cut cavity.