Patents Examined by Mamadou Diallo
  • Voltage regulation of device functional properties
    Patent number: 9799825
    Abstract: Systems, methods, and apparatus are provided for tuning a functional property of a device. The device (210) includes a layer of a dielectric material (214) disposed over and forming an interface (216) with a layer of an electrically conductive target material (222). The dielectric material layer includes at least one ionic species having a high ion mobility. The target material is configured such that a potential difference applied to the device can cause the at least one ionic species to migrate reversibly across the interface into or out of the target material layer. The mobility of the at least one ionic species can be tuned by exposing the device to electromagnetic radiation and/or a temperature change.
    Type: Grant
    Filed: March 16, 2015
    Date of Patent: October 24, 2017
    Assignee: Massachusetts Institute of Technology
    Inventors: Uwe Bauer, Geoffrey S. D. Beach
  • Method for manufacturing memory device and method for manufacturing shallow trench isolation
    Patent number: 9799755
    Abstract: A method for manufacturing a memory device includes forming trenches in a substrate to define an active region, filling an insulation material in the trenches, treating at least one portion of the insulation material, removing an upper portion of the insulation material from the trenches, so as to expose upper portions of side surfaces of the active region and to convert remaining portions of the insulation material in the trenches to shallow trench isolation (STI) disposed on opposite sides of the active region, forming a lower oxide layer, a middle charge trapping layer, and an upper oxide layer which cover the exposed upper portions of the side surfaces of the active region, an upper surface of the active region between the side surfaces of the active region, and the STI, and forming a gate layer on the upper oxide layer.
    Type: Grant
    Filed: September 14, 2016
    Date of Patent: October 24, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Tsung-Yu Yang, Cheng-Bo Shu, Chung-Jen Huang, Jing-Ru Lin, Jui-Yu Pan, Yun-Chi Wu, Yueh-Chieh Chu
  • Preparing a semiconductor surface for epitaxial deposition
    Patent number: 9793104
    Abstract: Provided is a method of epitaxial deposition, which involves dry-etching a semiconductor substrate with a fluorine containing species and exposing the dry-etched substrate to hydrogen atoms, prior to epitaxially depositing a semiconductor layer to the surface of the substrate.
    Type: Grant
    Filed: January 28, 2016
    Date of Patent: October 17, 2017
    Assignee: AIXTRON SE
    Inventors: Maxim Kelman, Shahab Khandan, Scott Dunham, Tac van Huynh, Kenneth B. K. Teo
  • Display device and manufacturing method thereof
    Patent number: 9786694
    Abstract: A display device and a method of manufacturing the display device are provided. According to an exemplary embodiment, a display device includes: a substrate; a gate electrode disposed on the substrate; a semiconductor pattern disposed on the gate electrode; data wiring disposed on the semiconductor pattern and having a data line, a source electrode, and a drain electrode; a first barrier layer disposed between the data wiring and the semiconductor pattern; and undercuts disposed on at least one side of each segment of the first barrier layer.
    Type: Grant
    Filed: September 13, 2016
    Date of Patent: October 10, 2017
    Assignee: Samsung Display Co., Ltd.
    Inventors: Gwang Min Cha, Su Kyoung Yang, Chan Woo Yang
  • Structure and method for improved stabilization of cobalt cap and/or cobalt liner in interconnects
    Patent number: 9780035
    Abstract: A method for fabricating a metallization layer of a semiconductor device, in which copper is used for an interconnect material and cobalt is used to encapsulate the copper, includes introducing a material that will form an alloy with cobalt and resist a degradation of an effect of the cobalt on encapsulating the copper.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: October 3, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Benjamin David Briggs, James J. Kelly, Koichi Motoyama, Roger Allan Quon, Michael Rizzolo, Theodorus Eduardus Standaert
  • Organic electroluminescence device with separating foil
    Patent number: 9780330
    Abstract: The invention relates to OLEDs (1) having a substrate (2), a first electrode layer (3), a layer of organic electroluminescence material (4), a second electrode layer (5), a cover layer (6), moisture-absorbing means (9) and a separating foil (10) of resilient material. According to the invention, said foil (10) is positioned between the second electrode layer (5) and the moisture-absorbing means (9). This feature results in a longer mean life-time of the OLED. Advantageously spacer structures (12) (preferably formed as dots) are applied on the separating foil (10) between the foil (10) and the cover (6). This prevents discoloring effects around the rim of the OLED material.
    Type: Grant
    Filed: July 5, 2016
    Date of Patent: October 3, 2017
    Assignee: KONINKLIJKE PHILIPS N.V.
    Inventors: Herbert Friedrich Boerner, Rainald Manfred Gierth, Stefan Peter Grabowski, Petrus Cornelis Paulus Bouten, Peter Van De Weijer
  • Semiconductor device with magnetically aligned chips and method for fabricating the same
    Patent number: 9773758
    Abstract: A semiconductor device includes a first semiconductor chip adjacent a second semiconductor chip. The first semiconductor chip includes a first surface and a second surface. The second semiconductor chip includes a third surface and a fourth surface. The third surface faces the second surface. A first through-electrode and a second through-electrode are between the first and second surfaces. A third through-electrode is between the third surface and the fourth surface and is connected to the first through-electrode. A fourth through-electrode is between the third surface and the fourth surface and is connected to the second through-electrode. An end of the first through-electrode has a first magnetic polarity on the second surface, and an end of the second through-electrode has a second magnetic polarity opposite to the first magnetic polarity on the second surface.
    Type: Grant
    Filed: September 14, 2016
    Date of Patent: September 26, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Ji Young Kim
  • Film for semiconductor back surface and its use
    Patent number: 9768050
    Abstract: It is an object of the present invention to provide a film for semiconductor back surface having reworkability, and an application of the film. A film for semiconductor back surface has: an adhering strength at 70° C. of 7 N/10 mm or less to a wafer before the film is thermally cured; and a rupture elongation at 25° C. of 700% or less. The film for semiconductor back surface preferably has a degree of swelling due to ethanol of 1% by weight or more. The film for semiconductor back surface preferably contains an acrylic resin.
    Type: Grant
    Filed: May 31, 2016
    Date of Patent: September 19, 2017
    Assignee: NITTO DENKO CORPORATION
    Inventors: Naohide Takamoto, Ryuichi Kimura
  • Semiconductor device and method fabricating the same
    Patent number: 9768112
    Abstract: According to an exemplary embodiment, a semiconductor device is provided. The semiconductor device includes a first seal ring and a first circuit. The first circuit includes a first capacitor and a first inductor connected in series. The first circuit is connected between the first seal ring and a ground.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: September 19, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Hsiao-Chun Lee, Chi-Feng Huang, Victor Chiang Liang
  • Semiconductor memory
    Patent number: 9768188
    Abstract: A semiconductor memory includes a memory cell region that includes multiple memory cells stacked above a semiconductor substrate, first and second dummy regions on opposite sides of the memory cell region, each dummy region including multiple dummy cells stacked above the semiconductor substrate, and a wiring that electrically connects dummy cells of the first and second dummy regions that are at a same level above the semiconductor substrate.
    Type: Grant
    Filed: November 11, 2016
    Date of Patent: September 19, 2017
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Tomoo Hishida, Sadatoshi Murakami, Ryota Katsumata, Masao Iwase
  • Low-k dielectric interconnect systems
    Patent number: 9768061
    Abstract: A method of fabricating a semiconductor device includes forming a low-k dielectric layer over a substrate and depositing a cap layer over the low-k dielectric layer. A treatment process is performed to the cap layer. After the treatment process to the cap layer is performed, the low-k dielectric layer is etched to form a plurality of trenches using the cap layer as an etching mask.
    Type: Grant
    Filed: May 31, 2016
    Date of Patent: September 19, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Po-Cheng Shih, Chia Cheng Chou, Chung-Chi Ko
  • Display panel, display unit, and electronic apparatus
    Patent number: 9767724
    Abstract: A display panel includes a plurality of pixels and a plurality of power lines. The plurality of pixels are disposed in a matrix and include respective light-emitting devices and respective pixel circuits. The pixel circuits are disposed at unequal intervals in a column direction. The light-emitting devices are provided to allow light-emitting regions of the respective light-emitting devices to have an equal interval in the column direction. The plurality of power lines are extended in a row direction and each supply a current flowing into the light-emitting device. Each one of the plurality of power lines is disposed for a plurality of pixel rows. A spacing between the pixel circuits in the column direction is relatively large at a portion facing one of the power lines. A spacing between the pixel circuits in the column direction is relatively small at a portion facing wiring other than the power lines.
    Type: Grant
    Filed: November 10, 2016
    Date of Patent: September 19, 2017
    Assignee: JOLED Inc.
    Inventor: Tetsuro Yamamoto
  • Method of manufacturing thin film transistor, thin film transistor manufactured by the method, and electronic device comprising the thin film transistor
    Patent number: 9761818
    Abstract: A method of manufacturing a thin film transistor includes forming a gate electrode, forming a gate insulating layer on the gate electrode, forming an organic semiconductor layer on the gate insulating layer, forming a solvent selective photosensitive layer on the organic semiconductor layer, forming an organic semiconductor pattern and a solvent selective photosensitive pattern by simultaneously patterning the organic semiconductor layer and the solvent selective photosensitive layer, respectively, and forming a source electrode and a drain electrode on the organic semiconductor pattern and the solvent selective photosensitive pattern, the source electrode and the drain electrode being electrically connected to the organic semiconductor pattern.
    Type: Grant
    Filed: May 31, 2016
    Date of Patent: September 12, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Youngjun Yun, Joo Young Kim, Byong Gwon Song, Jaewon Jang, Jiyoung Jung, Ajeong Choi
  • Layout of transmission vias for memory device
    Patent number: 9761564
    Abstract: Apparatuses and methods for supplying power to a plurality of dies are described. An example apparatus includes: a substrate; first, second and third memory cell arrays arranged in line in a first direction in the substrate; a first set of through electrodes arranged between the first and second memory cell arrays, each of the first set of through electrodes penetrating through the substrate, the first set of through electrodes including first and second through electrodes; and a second set of through electrodes arranged between the second and third memory cell arrays, each of the second set of through electrodes penetrating through the substrate, the second set of through electrodes including third and fourth through electrodes.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: September 12, 2017
    Assignee: Micron Technology, Inc.
    Inventor: Kayoko Shibata
  • Bond chuck, methods of bonding, and tool including bond chuck
    Patent number: 9754813
    Abstract: A bonding chuck is discussed with methods of using the bonding chuck and tools including the bonding chuck. A method includes loading a first wafer on first surface of a first bonding chuck, loading a second wafer on a second bonding chuck, and bonding the first wafer to the second wafer. The first surface is defined at least in part by a first portion of a first spherical surface and a second portion of a second spherical surface. The first spherical surface has a first radius, and the second spherical surface has a second radius. The first radius is less than the second radius.
    Type: Grant
    Filed: November 2, 2016
    Date of Patent: September 5, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hui Huang, Yen-Chang Chu, Kuan-Liang Liu, Ping-Yin Liu, Cheng-Yuan Tsai, Yeur-Luen Tu, Chia-Shiung Tsai, Ru-Liang Lee
  • Method and equipment for treating a precursor of a heterojunction photovoltaic cell and associated method for producing a photovoltaic cell
    Patent number: 9755102
    Abstract: The precursor comprises at least one layer of doped crystalline silicon and a layer of doped amorphous semiconductor material. The method comprises the steps of placing the cell precursor sandwiched between a grounded conducting plate and a plate made of insulating material coated with a conducting layer, then applying a state change electrical voltage (U1) between the conducting layer and ground, the said state change electrical voltage (U1) being designed to bring the Fermi level at the interface between crystalline silicon and amorphous semiconductor material closer to the middle of the band gap of the said amorphous semiconductor material, while at the same time heating the cell precursor to a defect equilibration temperature (TE), and finally cooling down the cell precursor (10) prior to interrupting the application of the state change electrical voltage (U1).
    Type: Grant
    Filed: March 23, 2015
    Date of Patent: September 5, 2017
    Assignee: COMMISSARIAT A L'ENERGIE ATOMOIQUE ET AUX ENERGIES ALTERNATIVES
    Inventor: Renaud Varache
  • Method for evaluating semiconductor substrate
    Patent number: 9748151
    Abstract: The present invention provides a method for evaluating a semiconductor substrate subjected to a defect recovery heat treatment to recover a crystal defect in the semiconductor substrate having the crystal defect, flash lamp annealing is performed as the defect recovery heat treatment, and the method includes steps of measuring the crystal defect in the semiconductor substrate, which is being recovered, by controlling treatment conditions for the flash lamp annealing and analyzing a recovery mechanism of the crystal defect on the basis of a result of the measurement. Consequently, the method for evaluating a semiconductor substrate which enables evaluating a recovery process of the crystal defect is provided.
    Type: Grant
    Filed: February 23, 2015
    Date of Patent: August 29, 2017
    Assignee: SHIN-ETSU HANDOTAI CO., LTD.
    Inventors: Tsuyoshi Ohtsuki, Hiroshi Takeno
  • Compound, material for organic electroluminescence element, organic electroluminescence element, and electronic apparatus
    Patent number: 9748494
    Abstract: A compound is represented by a formula (1) below. In the formula (1), n is 1 or 2. Ar1 is represented by a formula (2) below. Ar2 represents a substituted or unsubstituted aromatic hydrocarbon group having 6 to 30 carbon atoms, or a substituted or unsubstituted heterocyclic group having 1 to 20 ring atoms. Ar3 is represented by a formula (3) below.
    Type: Grant
    Filed: July 1, 2014
    Date of Patent: August 29, 2017
    Assignee: IDEMITSU KOSAN CO., LTD.
    Inventors: Hirokatsu Ito, Tomohiro Nagao
  • Semiconductor die with backside protection
    Patent number: 9741671
    Abstract: A semiconductor die with backside protection includes an active region and a first polysilicon layer formed on a front side of a semiconductor substrate. A signal net is connected to the first polysilicon layer by way of a metal contact and a conductive wire is formed above the active region. During an invasive attack, when a trench is formed in the substrate and an electrically conductive filling is deposited in the trench, the signal net, the conductive wire, and the first polysilicon shape form a short-circuit, which renders the die dysfunctional and thereby foiling the invasive attack.
    Type: Grant
    Filed: November 10, 2016
    Date of Patent: August 22, 2017
    Assignee: NXP B.V.
    Inventors: Sven Trester, Claus Grzyb
  • Hydrogen free amorphous silicon as insulating dielectric material for superconducting quantum bits
    Patent number: 9741921
    Abstract: A hydrogen-free amorphous dielectric insulating film having a high material density and a low density of tunneling states. The film is prepared by deposition of a dielectric material on a substrate having a high substrate temperature Tsub under high vacuum and at a controlled low deposition rate. In one embodiment, the film is amorphous silicon while in another embodiment the film is amorphous germanium.
    Type: Grant
    Filed: November 16, 2016
    Date of Patent: August 22, 2017
    Assignee: The United States of America as represented by the Secretary of the Navy
    Inventors: Xiao Liu, Daniel R. Queen, Frances Hellman, Thomas H. Metcalf, Matthew R. Abernathy, Glenn G. Jernigan