Patents Examined by Marc-Anthony Armand
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Patent number: 11616142Abstract: A semiconductor device and method of manufacturing the semiconductor device are provided. An exemplary semiconductor device comprises a fin disposed over a substrate, wherein the fin includes a channel region and a source/drain region; a gate structure disposed over the substrate and over the channel region of the fin; a source/drain feature epitaxially grown in the source/drain region of the fin, wherein the source/drain feature includes a top epitaxial layer and a lower epitaxial layer formed below the top epitaxial layer, and the lower epitaxial layer includes a wavy top surface; and a contact having a wavy bottom surface matingly engaged with the wavy top surface of the lower epitaxial layer of the source/drain feature.Type: GrantFiled: December 6, 2021Date of Patent: March 28, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chia-Ta Yu, Yen-Chieh Huang, Wei-Yuan Lu, Feng-Cheng Yang, Yen-Ming Chen
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Patent number: 11611032Abstract: A novel and useful modified semiconductor fabrication technique for realizing reliable semiconductor quantum structures. Quantum structures require a minimization of the parasitic capacitance of the control gate and the quantum well. The modified semiconductor process eliminates the fabrication of the metal, contact, and optionally the raised diffusion layers from the quantum wells, thereby resulting in much lower well and gate capacitances and therefore larger Coulomb blockade voltages. This allows easier implementation of the electronic control circuits in that they can have larger intrinsic noise and relaxed analog resolution. Several processes are disclosed including implementations of semiconductor quantum structures with tunneling through an oxide layer as well as tunneling through a local well depleted region. These techniques can be used in both planar semiconductor processes and 3D, e.g., FinFET, semiconductor processes. A dedicated process masking step is used for realizing the raised diffusions.Type: GrantFiled: January 25, 2021Date of Patent: March 21, 2023Assignee: Equal1.Labs Inc.Inventors: Dirk Robert Walter Leipold, George Adrian Maxim, Michael Albert Asker
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Patent number: 11605634Abstract: A device is provided. The device includes an interfacial layer on a semiconductor device channel. The device further includes a dipole layer on the interfacial layer, and a gate dielectric layer on the dipole layer. The device further includes a first work function layer associated with a first field effect transistor device; and a second work function layer associated with a second field effect transistor device, such that the first field effect transistor device and second field effect transistor device each have a different threshold voltage than a first field effect transistor device and second field effect transistor device without a dipole layer.Type: GrantFiled: September 22, 2021Date of Patent: March 14, 2023Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Ruqiang Bao, Koji Watanabe
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Patent number: 11605598Abstract: A semiconductor device package includes a substrate having a surface, a conductive element disposed on the surface of the substrate, and an encapsulant disposed on the surface of the substrate and covering the conductive element. The conductive element has an upper surface facing away from the substrate and exposed from the encapsulant. Further, a roughness of the upper surface of the conductive element is greater than a roughness of a side surface of the conductive element.Type: GrantFiled: April 17, 2020Date of Patent: March 14, 2023Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Wei Da Lin, Meng-Jen Wang, Hung Chen Kuo, Wen Jin Huang
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Patent number: 11600662Abstract: Data storage devices are provided. A data storage device includes a memory transistor on a substrate and a data storage structure electrically connected to the memory transistor. The data storage structure includes a magnetic tunnel junction pattern and a top electrode on the magnetic tunnel junction pattern. The top electrode includes a first top electrode and a second top electrode on the first top electrode, and the first and second top electrodes include the same metal nitride. The first top electrode includes first crystal grains of the metal nitride, and the second top electrode includes second crystal grains of the metal nitride. In a section of the top electrode, the number of the first crystal grains per a unit length is greater than the number of the second crystal grains per the unit length.Type: GrantFiled: January 24, 2022Date of Patent: March 7, 2023Inventors: Junghwan Park, Younghyun Kim, Se Chung Oh, Jungmin Lee, Kyungil Hong
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Patent number: 11600561Abstract: A semiconductor device includes a semiconductor element, a first lead including a mounting portion for the semiconductor element and a first terminal portion connected to the mounting portion, and a sealing resin covering the semiconductor element and a portion of the first lead. The mounting portion has a mounting-portion front surface and a mounting-portion back surface opposite to each other in a thickness direction, with the semiconductor element mounted on the mounting-portion front surface. The sealing resin includes a resin front surface, a resin back surface and a resin side surface connecting the resin front surface and the resin back surface. The mounting-portion back surface of the first lead is flush with the resin back surface. The first terminal portion includes a first-terminal-portion back surface exposed from the resin back surface, in a manner such that the first-terminal-portion back surface extends to the resin side surface.Type: GrantFiled: December 13, 2021Date of Patent: March 7, 2023Assignee: ROHM CO., LTD.Inventors: Koshun Saito, Yasufumi Matsuoka
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Patent number: 11598884Abstract: A navigational apparatus and method for augmenting a GNSS signal to the GPS simulator with alternative position, navigation, or timing (PNT) data, wherein the GPS simulator encodes an RF-simulated GPS signal based on the alternative PNT data when the GNSS signal is not available or is denied. The alternative PNT data may be provided by one or more of an Inertial Measurement Unit, Inertial Navigation System (IMU/INS) module and oscillator coupled to the GPS simulator.Type: GrantFiled: December 3, 2021Date of Patent: March 7, 2023Assignee: Viavi Solutions, Inc.Inventors: Gregor Said Jackson, Giovanni D'andrea
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Patent number: 11594616Abstract: The structure of a semiconductor device with negative capacitance (NC) dielectric structures and a method of fabricating the semiconductor device are disclosed. A method of fabricating the semiconductor device includes forming a fin structure with a fin base portion and a fin top portion on a substrate, forming a spacer structure in a first region of the fin top portion, and forming a gate structure on a second region of the fin top portion. The spacer structure includes a first NC dielectric material and the gate structure includes a gate dielectric layer with a second NC dielectric material different from the first NC dielectric material.Type: GrantFiled: August 23, 2021Date of Patent: February 28, 2023Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chansyun David Yang, Keh-Jeng Chang, Chan-Lon Yang
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Patent number: 11594596Abstract: Embodiments of the present invention are directed to a back-end-of-line (BEOL) compatible metal-insulator-metal on-chip decoupling capacitor (MIMCAP). This BEOL compatible process includes a thermal treatment for inducing an amorphous-to-cubic phase change in the insulating layer of the MIM stack prior to forming the top electrode. In a non-limiting embodiment of the invention, a bottom electrode layer is formed, and an insulator layer is formed on a surface of the bottom electrode layer. The insulator layer can include an amorphous dielectric material. The insulator layer is thermally treated such that the amorphous dielectric material undergoes a cubic phase transition, thereby forming a cubic phase dielectric material. A top electrode layer is formed on a surface of the cubic phase dielectric material of the insulator layer.Type: GrantFiled: March 3, 2021Date of Patent: February 28, 2023Assignee: International Business Machines CorporationInventors: Paul Jamison, Takashi Ando, John Greg Massey, Eduard Cartier
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Patent number: 11569233Abstract: Techniques and mechanisms for operating transistors that are in a stacked configuration. In an embodiment, an integrated circuit (IC) device includes transistors arranged along a line of direction which is orthogonal to a surface of a semiconductor substrate. A first epitaxial structure and a second epitaxial structure are coupled, respectively, to a first channel structure of a first transistor and a second channel structure of a second transistor. The first epitaxial structure and the second epitaxial structure are at different respective levels relative to the surface of the semiconductor substrate. A dielectric material is disposed between the first epitaxial structure and the second epitaxial structure to facilitate electrical insulation of the channels from each other. In another embodiment, the stacked transistors are coupled to provide a complementary metal-oxide-semiconductor (CMOS) inverter circuit.Type: GrantFiled: May 28, 2021Date of Patent: January 31, 2023Assignee: Intel CorporationInventors: Ravi Pillarisetty, Willy Rachmady, Marko Radosavljevic, Van H. Le, Jack T. Kavalieros
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Patent number: 11569294Abstract: A semiconductor device includes a semiconductor substrate and an interconnection region disposed on the semiconductor substrate. The interconnection region includes stacked metallization levels, a magnetic tunnel junction, and a transistor. The magnetic tunnel junction is formed on a first conductive pattern of a first metallization level of the stacked metallization levels. The transistor is formed on a second conductive pattern of a second metallization level of the stacked metallization levels. The transistor is a vertical gate-all-around transistor. A drain contact of the transistor is electrically connected to the magnetic tunnel junction by the first conductive pattern of the first metallization level. The second metallization level is closer to the semiconductor substrate than the first metallization level.Type: GrantFiled: July 8, 2020Date of Patent: January 31, 2023Assignee: Taiwan Semiconductor Manufacturing Company Ltd.Inventors: Mauricio Manfrini, Chung-Te Lin, Ken-Ichi Goto
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Patent number: 11569193Abstract: A semiconductor package may include a semiconductor chip on a package substrate. The semiconductor package may include a plurality of conductive connections connecting the semiconductor chip to the package substrate may be disposed, a plurality of towers which are apart from one another and each include a plurality of memory chips may be disposed, wherein a lowermost memory chip of each of the plurality of towers overlaps the semiconductor chip from a top-down view. The semiconductor package further includes a plurality of adhesive layers be attached between the lowermost memory chip of each of the plurality of towers and the semiconductor chip.Type: GrantFiled: April 6, 2021Date of Patent: January 31, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hyungu Kang, Jaekyu Sung
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Patent number: 11563085Abstract: Structures for a field-effect transistor and methods of forming a structure for a field-effect transistor. A gate structure is arranged over a channel region of a semiconductor body. A first source/drain region is coupled to a first portion of the semiconductor body, and a second source/drain region is located in a second portion the semiconductor body. The first source/drain region includes an epitaxial semiconductor layer containing a first concentration of a dopant. The second source/drain region contains a second concentration of the dopant. The channel region is positioned in the semiconductor body between the first source/drain region and the second source/drain region.Type: GrantFiled: April 29, 2021Date of Patent: January 24, 2023Assignee: GlobalFoundries U.S. Inc.Inventors: Jiehui Shu, Baofu Zhu, Haiting Wang, Sipeng Gu
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Patent number: 11557547Abstract: A leadframe for semiconductor devices, the leadframe comprising a die pad portion having a first planar die-mounting surface and a second planar surface opposed the first surface, the first surface and the second surface having facing peripheral rims jointly defining a peripheral outline of the die pad wherein the die pad comprises at least one package molding compound receiving cavity opening at the periphery of said first planar surface.Type: GrantFiled: December 18, 2020Date of Patent: January 17, 2023Assignee: STMicroelectronics S.r.l.Inventors: Roberto Tiziani, Mauro Mazzola
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Patent number: 11557610Abstract: A semiconductor integrated circuit device including a plurality of rows of IO cells has a configuration capable of avoiding a latchup error without causing an increase in area. The device includes a first IO cell row placed closest to an edge of a chip and a second IO cell row placed adjacent to a core region side of the first IO cell row. Each of the IO cells of the first and second IO cell rows has a high power supply voltage region and a low power supply voltage region provided separately in a direction perpendicular to a direction in which the IO cells are lined up. The IO cell rows are placed so that the high power supply voltage regions of these rows are mutually opposed.Type: GrantFiled: July 26, 2021Date of Patent: January 17, 2023Assignee: SOCIONEXT INC.Inventor: Isaya Sobue
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Patent number: 11552077Abstract: A method of forming a power rail to semiconductor devices comprising removing a portion of the gate structure forming a gate cut trench separating a first active region of fin structures from a second active region of fin structures. A conformal etch stop layer is formed in the gate cut trench. A fill material is formed on the conformal etch stop layer filling at least a portion of the gate cut trench. The fill material has a composition that is etched selectively to the conformal etch stop layer. A power rail is formed in the gate cut trench. The conformal etch stop layer obstructs lateral etching during forming the power rail to substantially eliminate power rail to gate structure shorting.Type: GrantFiled: April 2, 2021Date of Patent: January 10, 2023Assignee: TESSERA LLCInventors: Marc A. Bergendahl, Andrew M. Greene, Rajasekhar Venigalla
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Patent number: 11545446Abstract: A semiconductor device includes a semiconductor element, a lead frame, a conductive member, a resin composition and a sealing resin. The semiconductor element has an element front surface and an element back surface facing away in a first direction. The semiconductor element is mounted on the lead frame. The conductive member is bonded to the lead frame, electrically connecting the semiconductor element and the lead frame. The resin composition covers a bonded region where the conductive member and lead frame are bonded while exposing part of the element front surface. The sealing resin covers part of the lead frame, the semiconductor element, and the resin composition. The resin composition has a greater bonding strength with the lead frame than a bonding strength between the sealing resin and lead frame and a greater bonding strength with the conductive member than a bonding strength between the sealing resin and conductive member.Type: GrantFiled: July 18, 2019Date of Patent: January 3, 2023Assignee: ROHM CO., LTD.Inventors: Hidetoshi Abe, Makoto Ikenaga, Kensei Takamoto
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Patent number: 11545454Abstract: A semiconductor device includes an insulating layer, a barrier electrode layer formed on the insulating layer, a Cu electrode layer that includes a metal composed mainly of copper and that is formed on a principal surface of the barrier electrode layer, and an outer-surface insulating film that includes copper oxide, that coats an outer surface of the Cu electrode layer, and that is in contact with the principal surface of the barrier electrode layer.Type: GrantFiled: April 14, 2021Date of Patent: January 3, 2023Assignee: ROHM CO., LTD.Inventors: Bungo Tanaka, Keiji Wada, Satoshi Kageyama
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Patent number: 11538986Abstract: A storage layer of a magnetic tunnel junction (MTJ) element is disclosed. The storage layer having perpendicular magnetic anisotropy includes a first ferromagnetic layer, a first dust layer disposed directly on the first ferromagnetic layer, a second ferromagnetic layer disposed directly on the first dust layer, a second dust layer disposed directly on the second ferromagnetic layer, and a third ferromagnetic layer disposed directly on the second dust layer. A material of the first dust layer is different from a material of the second dust layer.Type: GrantFiled: April 15, 2020Date of Patent: December 27, 2022Assignee: HeFeChip Corporation LimitedInventors: Qinli Ma, Wei-Chuan Chen, Shu-Jen Han
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Patent number: 11531084Abstract: A radar system is generated by a process including generating a first substrate layer adjacent to a ground plane of a patch antenna array in the radar system, etching an opening in the substrate layer, inserting a mechanically-locking foot of a threaded insert into the opening, adding a second substrate layer adjacent to the first substrate layer to embed the threaded insert, applying a thermal coupling between a heat sink layer and the second substrate layer of the radar system and screwing a screw through the heat sink layer and into the threaded insert to adhere the heat sink layer to the radar system. Such a radar system can enable the attachment of the heat sink layer to the radar system in a removable fashion such that the heat sink layer can be removed by removing the screw and repairs can be done without damaging respective layers.Type: GrantFiled: April 3, 2020Date of Patent: December 20, 2022Assignee: Fortem Technologies, Inc.Inventors: David Earl James, Jon Erik Knabenschuh, Matthew Robertson Morin, James David Mackie, Chester Parker Ferry, Brandon Robert Hicks, Kendall James Fowkes, James Harrison Hofer, Jr.