Patents Examined by Mary Wilczewski
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Patent number: 10854713Abstract: A method includes forming a flowable dielectric layer in a trench of a substrate; curing the flowable dielectric layer; and annealing the cured flowable dielectric layer to form an insulation structure and a liner layer. The insulation structure is formed in the trench, the liner layer is formed between the insulation structure and the substrate, and the liner layer includes nitrogen.Type: GrantFiled: January 8, 2018Date of Patent: December 1, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Jia-Ming Lin, Shiu-Ko Jangjian, Chun-Che Lin, Ying-Lang Wang, Wei-Ken Lin, Chuan-Pu Liu
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Patent number: 10854761Abstract: A electrical switch has a first substrate, a first conducting layer disposed on the first substrate, a first dielectric layer disposed on the first conducting layer and a second conducting layer disposed on the first dielectric layer, and the second conducting layer disposed on the second substrate, and a conductive via connected to the first conducting layer and extending through the first dielectric layer. Active dielectric has a first conductor, a first dielectric layer disposed on the first conducting layer, one or more electrical switches disposed on the first dielectric layer, a dielectric layer disposed between neighboring electrical switches, the second dielectric layer disposed on the last electrical switch, and the second conducting layer disposed on the second dielectric layer.Type: GrantFiled: March 30, 2016Date of Patent: December 1, 2020Assignee: Southern Methodist UniversityInventors: Choon Sae Lee, Daivd A. Willis, Yang Fan
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Patent number: 10854759Abstract: A trenched MOS gate controlled rectifier has an asymmetric trench structure between the active area of active trenches and the termination area of termination trenches. The asymmetric trench structure has a gate electrode on one side of the trench to turn on and off the channel of the MOS structure effectively and a field plate structure on the other side with field dielectric sufficiently thick in order to sustain the high electric field during the reverse bias condition.Type: GrantFiled: April 1, 2016Date of Patent: December 1, 2020Assignee: Diodes IncorporatedInventors: Peter Hugh Blair, Lee Spencer Riley
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Patent number: 10847612Abstract: A method of manufacturing a memory structure including the following steps is provided. Stacked structures are formed on a substrate, and each of the stacked structures includes a first dielectric layer and a first conductive layer sequentially disposed on the substrate. A first opening is located between two adjacent stacked structure, and the first opening extends into the substrate. At least one isolation structure is formed in the first opening. The isolation structure covers a sidewall of the first dielectric layer. The isolation structure has a recess therein, such that a top profile of the isolation structure is shaped as a funnel. A second dielectric layer is formed on the stacked structures. A second conductive layer is formed on the second dielectric layer and fills the first opening.Type: GrantFiled: July 18, 2019Date of Patent: November 24, 2020Assignee: Winbond Electronics Corp.Inventors: Chung-Hsien Liu, Chun-Hsu Chen, Lu-Ping Chiang
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Patent number: 10847592Abstract: An electroluminescent display device includes a substrate; a pixel having a first lateral side and a second lateral side that intersects the first lateral side, the pixel including an emitting diode disposed over the substrate, the emitting diode including a first electrode, an emitting layer on the first electrode, and a second electrode on the emitting layer; an insulating pattern overlapping the first lateral side of the pixel and covering a first end of the first electrode at the first lateral side of the pixel; and a bank surrounding the pixel, wherein the bank overlaps the insulating pattern at the first lateral side of the pixel, and the bank at the second lateral side of the pixel covers a second end of the first electrode.Type: GrantFiled: December 6, 2018Date of Patent: November 24, 2020Assignee: LG Display Co., Ltd.Inventors: Kang-Hyun Kim, Geum-Young Lee
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Patent number: 10840226Abstract: A light-emitting apparatus includes a plurality of packages each including a first substrate, and a single second substrate on which the plurality of packages are arrayed. The first substrate includes a first light source and a second light source. The first light source includes a first light-emitting section that emits light having a first wavelength, and first and second electrodes that are coupled to the first light-emitting section. The second light source includes a second light-emitting section that emits light having a second wavelength, and third and fourth electrodes that are coupled to the second light-emitting section. The second substrate includes first connection which is coupled to both the first electrode in a first package and the first electrode in a second package, second connection coupled to both the third electrode in the first package and the third electrode in the second package, and a driving circuit.Type: GrantFiled: September 8, 2016Date of Patent: November 17, 2020Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventor: Goshi Biwa
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Patent number: 10840411Abstract: A semiconductor layer sequence is disclosed. In an embodiment the semiconductor layer sequence includes an n-conducting n-region, a p-conducting p-region and an active zone having at least one quantum well located between the n-region and the p-region, wherein the semiconductor layer sequence includes AlInGaN, wherein the n-region comprises a superlattice, wherein the superlattice has a structural unit which repeats at least three times, wherein the structural unit comprises at least one AlGaN layer, at least one GaN layer and at least one InGaN layer, wherein an intermediate layer is disposed between the active zone and the superlattice, wherein the intermediate layer comprises either n-doped GaN or n-doped GaN together with n-doped InGaN so that the intermediate layer is free of aluminum, and wherein the intermediate layer directly adjoins the active zone and the superlattice.Type: GrantFiled: July 5, 2017Date of Patent: November 17, 2020Assignee: OSRAM OLED GmbHInventor: Werner Bergbauer
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Patent number: 10832914Abstract: In a vertical MOSFET of a trench gate structure, a high-concentration implantation region is provided in a p-type base region formed from a p-type silicon carbide layer formed by epitaxial growth, so as to include a portion in which a channel is formed. The high-concentration implantation region is formed by ion implantation of a p-type impurity into the p-type silicon carbide layer. The high-concentration implantation region is formed by p-type ion implantation and has an impurity concentration profile in which concentration differences in a depth direction form a bell-shaped curve at a peak of impurity concentration that is higher than that of the p-type silicon carbide layer. In the p-type base region, disorder occurs partially in the crystal structure consequent to the ion implantation for forming the high-concentration implantation region.Type: GrantFiled: June 18, 2019Date of Patent: November 10, 2020Assignee: FUJI ELECTRIC CO., LTD.Inventors: Setsuko Wakimoto, Masanobu Iwaya
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Patent number: 10833161Abstract: A semiconductor device includes: (i) a substrate; (ii) a first elongated semiconductor structure extending in a first horizontal direction along the substrate and protruding vertically above the substrate, wherein a first set of source/drain regions are formed on the first semiconductor structure; (iii) a second elongated semiconductor structure extending along the substrate in parallel to the first semiconductor structure and protruding vertically above the substrate, wherein a second set of source/drain regions are formed on the second semiconductor structure; and (iv) a first set of source/drain contacts formed on the first set of source/drain regions, wherein a first source/drain contact of the first set of source/drain contacts includes: (a) a vertically extending contact portion formed directly above a first source/drain region of the first set of source/drain regions, and (b) a via landing portion protruding horizontally from the vertically extending contact portion in a direction towards the second seType: GrantFiled: January 22, 2019Date of Patent: November 10, 2020Assignees: IMEC VZW, GLOBALFOUNDRIES INC.Inventors: Syed Muhammad Yasser Sherazi, Julien Ryckaert, Juergen Boemmels, Guillaume Bouche
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Patent number: 10825954Abstract: A light-emitting device may include a semiconductor body having a first conductivity type, with a front side and a back side. The light-emitting device may also include a porous-silicon region which extends in the semiconductor body at the front side, and a cathode region in direct lateral contact with the porous-silicon region. The light-emitting device may further include a barrier region of electrically insulating material, which extends in direct contact with the cathode region at the bottom side of the cathode region so that, in use, an electric current flows in the semiconductor body through lateral portions of the cathode region.Type: GrantFiled: May 18, 2018Date of Patent: November 3, 2020Assignee: STMICROELECTRONICS S.R.L.Inventors: Marco Morelli, Fabrizio Fausto Renzo Toia, Giuseppe Barillaro, Marco Sambi
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Patent number: 10825816Abstract: A recessed access device comprises a conductive gate in a trench in semiconductor material. A gate insulator is along sidewalls and a base of the trench between the conductive gate and the semiconductor material. A pair of source/drain regions is in upper portions of the semiconductor material on opposing sides of the trench. A channel region is in the semiconductor material below the pair of source/drain regions along the trench sidewalls and around the trench base. At least some of the channel region comprises GaP.Type: GrantFiled: February 15, 2018Date of Patent: November 3, 2020Assignee: Micron Technology, Inc.Inventors: Yunfei Gao, Richard J. Hill, Gurtej S. Sandhu, Haitao Liu, Deepak Chandra Pandey, Srinivas Pulugurtha, Kamal M. Karda
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Patent number: 10804488Abstract: An organic electroluminescent device with a touch sensor including: a first substrate; a second substrate arranged opposite to the first substrate; an organic EL element layer arranged above the first substrate; a first sealing film arranged toward the second substrate of the organic EL element layer, covering the organic EL element layer, and including a first inorganic layer; plural first detection electrodes extending in one direction, and arranged in parallel toward the second substrate of the first sealing film; a second sealing film arranged toward the second substrate of the first detection electrodes, and including a second inorganic layer; plural second detection electrodes extending in another direction different from the one direction, and arranged in parallel toward the second substrate of the second sealing film; and a touch sensor control unit control ling a potential to detect a touch with a display surface.Type: GrantFiled: November 21, 2018Date of Patent: October 13, 2020Assignee: Japan Display Inc.Inventors: Toshihiro Sato, Ryoichi Ito
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Patent number: 10796985Abstract: A lead frame is provided, including one or more power terminals and one or more control terminals, wherein at least one of the control terminals is externally terminated with a press-fit contact member, and wherein at least one of the control terminals and at least one power terminals are formed from different materials. With the disclosed lead frame of the invention, lower material cross sections in the power terminals will be provided because of the better electrical conductivity when using pure copper compared to alloys with higher mechanical strengths. Also specific/different plating could be added to the individual needs of the different pin types without using masks in the plating process.Type: GrantFiled: June 21, 2017Date of Patent: October 6, 2020Assignee: Danfoss Silicon Power GmbHInventors: Holger Beer, Lars Paulsen
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Patent number: 10794853Abstract: The present disclosure relates to a method of depositing a polymer layer, including: providing a substrate, having a sensor structure disposed on the substrate, to a substrate support within a hot wire chemical vapor deposition (HWCVD) chamber; providing a process gas comprising an initiator gas and a monomer gas and a carrier gas to the HWCVD chamber; heating a plurality of filaments disposed in the HWCVD chamber to a first temperature sufficient to activate the initiator gas without decomposing the monomer gas; and exposing the substrate to initiator radicals from the activated initiator gas and to the monomer gas to deposit a polymer layer atop the sensor structure.Type: GrantFiled: December 6, 2017Date of Patent: October 6, 2020Assignee: APPLIED MATERIALS, INC.Inventors: Colin Neikirk, Yuriy Melnik, Pravin K. Narwankar
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Patent number: 10777426Abstract: A semiconductor device and method of formation are provided. The semiconductor device includes a first active region adjacent a channel, the channel, and a second active region adjacent the channel. The channel has a channel doping profile. The channel includes a central channel portion having a first dopant concentration of a first dopant and a radial channel portion surrounding the central channel portion. The radial channel portion has a second dopant concentration of a second dopant greater than the first dopant concentration. The channel comprising the central channel portion and the radial channel portion has increased voltage threshold tuning as compared to a channel that lacks a central channel portion and a radial channel portion.Type: GrantFiled: December 13, 2017Date of Patent: September 15, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITEDInventors: Yen-Ting Chen, I-Hsieh Wong, Chee-Wee Liu
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Patent number: 10777712Abstract: A semiconductor light-emitting device includes: a package substrate having a mounting surface on which a first circuit pattern and a second circuit pattern are disposed; a semiconductor LED chip mounted on the mounting surface, having a first surface which faces the mounting surface and on which a first electrode and a second electrode are disposed, a second surface opposing the first surface, and side surfaces located between the first surface and the second surface, the first electrode and the second electrode being connected to the first circuit pattern and the second circuit pattern, respectively; a wavelength conversion film disposed on the second surface; and a side surface inclined portion disposed on the side surfaces of the semiconductor LED chip, providing inclined surfaces, and including a light-transmitting resin containing a wavelength conversion material.Type: GrantFiled: August 22, 2018Date of Patent: September 15, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Mi Jeong Yun, Jong Sup Song
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Patent number: 10766769Abstract: A semiconductor element includes a processed substrate arrangement including a processed semiconductor substrate and a metallization layer arrangement on a main surface of the processed semiconductor substrate. The semiconductor element further includes a passivation layer arranged at an outer border of the processed substrate arrangement.Type: GrantFiled: March 22, 2018Date of Patent: September 8, 2020Assignee: Infineon Technologies AGInventors: Christian Bretthauer, Dirk Meinhold
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Patent number: 10756084Abstract: The present invention discloses a group-III nitride semiconductor device, which comprises a substrate, a buffer layer, a semiconductor stack structure, and a passivation film. The buffer layer is disposed on the substrate. The semiconductor stack structure is disposed on the buffer layer and comprises a gate, a source, and a drain. In addition, a gate insulating layer is disposed between the gate and the semiconductor stack structure for forming a HEMT. The passivation film covers the HEMT and includes a plurality of openings corresponding to the gate, the source, and the drain, respectively. The material of the passivation film is silicon oxynitride.Type: GrantFiled: June 2, 2017Date of Patent: August 25, 2020Inventor: Wen-Jang Jiang
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Patent number: 10748847Abstract: The present disclosure relates to a semiconductor device comprising a metallisation stack. The metallisation stack may include a first metallisation layer and a second metallisation layer. The first metallisation layer may be electrically connected to the second metallisation layer by a two or more stacked inter-metal vias.Type: GrantFiled: September 9, 2015Date of Patent: August 18, 2020Assignee: Nexperia B.V.Inventors: Paul Huiskamp, Godfried Henricus Josephus Notermans
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Patent number: 10749033Abstract: Disclosed is a semiconductor device including: an insulating layer; a source electrode and a drain electrode embedded in the insulating layer; an oxide semiconductor layer in contact and over the insulating layer, the source electrode, and the drain electrode; a gate insulating layer over and covering the oxide semiconductor layer; and a gate electrode over the gate insulating layer, where the upper surfaces of the insulating layer, the source electrode, and the drain electrode exist coplanarly. The upper surface of the insulating layer, which is in contact with the oxide semiconductor layer, has a root-mean-square (RMS) roughness of 1 nm or less, and the difference in height between the upper surface of the insulating layer and the upper surface of the source electrode or the drain electrode is less than 5 nm. This structure contributes to the suppression of defects of the semiconductor device and enables their miniaturization.Type: GrantFiled: February 4, 2014Date of Patent: August 18, 2020Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Hiromichi Godo, Ryota Imahayashi, Kiyoshi Kato