Abstract: A Field Effect Transistor (FET) device and a method for manufacturing it are disclosed. The FET device contains a graphene layer, a composite gate dielectric layer disposed above the graphene layer, wherein the composite gate layer is passivated with fluorine, and a metal gate disposed above the composite gate dielectric layer. The method disclosed teaches how to manufacture the FET device.

Abstract: Devices and techniques are provided for achieving OLED devices that include one or more plasmonic material exhibiting surface plasmon resonance and one or more outcoupling layers.

Abstract: A method for forming ultraviolet (UV) radiation responsive metal-oxide containing film is disclosed. The method may include, depositing an UV radiation responsive metal oxide-containing film over a substrate by, heating the substrate to a deposition temperature of less than 400° C., contacting the substrate with a first vapor phase reactant comprising a metal component, a hydrogen component, and a carbon component, and contacting the substrate with a second vapor phase reactant comprising an oxygen containing precursor, wherein regions of the UV radiation responsive metal oxide-containing film have a first etch rate after UV irradiation and regions of the UV radiation responsive metal oxide-containing film not irradiated with UV radiation have a second etch rate, wherein the second etch rate is different from the first etch rate.

Abstract: A display panel includes an upper display substrate and a lower display substrate. The upper display substrate includes a base substrate, a light shielding pattern, and including an opening part defined therein which corresponds to the pixel region, a color filter overlapped with the pixel region, an encapsulation layer disposed in lower sides of the light shielding pattern and the color filter, a partition wall disposed in a lower side of the encapsulation layer, overlapped with the light shielding region, and including a partition wall opening part defined therein which corresponds to the pixel region, and a quantum dot layer disposed inside the partition wall opening part. The partition wall includes a first layer directly disposed on the bottom surface of the encapsulation layer and a second layer directly disposed on a lower side of the first layer and having a larger optical density than the first layer.

Abstract: Ohmic contacts, including materials and processes for forming n-type ohmic contacts on n-type semiconductor substrates at low temperatures, are disclosed. Materials include reactant layers, n-type dopant layers, capping layers, and in some instances, adhesion layers. The capping layers can include metal layers and diffusion barrier layers. Ohmic contacts can be formed on n-type semiconductor substrates at temperatures between 150 and 250° C., and can resist degradation during operation.

Abstract: A display device includes: a substrate including a curved portion and a flat portion; an insulating layer disposed on the substrate; a first organic light emitting diode disposed on the insulating layer and having a first projection; and a second organic light emitting diode having a second projection, wherein a light emission portion is disposed in the curved portion and the flat portion, the first projection overlaps the light emission portion disposed in the curved portion and is asymmetric in the light emission portion, and the second projection overlaps the light emission portion in the flat portion and is symmetric in the light emission portion.

Abstract: Methods of semiconductor arrangement formation are provided. A method of forming the semiconductor arrangement includes forming a first nucleus on a substrate in a trench or between dielectric pillars on the substrate. Forming the first nucleus includes applying a first source material beam at a first angle relative to a top surface of the substrate and concurrently applying a second source material beam at a second angle relative to the top surface of the substrate. A first semiconductor column is formed from the first nucleus by rotating the substrate while applying the first source material beam and the second source material beam. Forming the first semiconductor column in the trench or between the dielectric pillars using the first source material beam and the second source material beam restricts the formation of the first semiconductor column to a single direction.

Abstract: A radiation-emitting semiconductor chip is disclosed. In an embodiment, a radiation-emitting semiconductor chip includes a semiconductor body configured to generate radiation, a first contact layer having a first contact area for external electrical contacting the semiconductor chip and a first contact finger structure connected to the first contact area, a second contact layer having a second contact area for external electrical contacting the semiconductor chip and a second contact finger structure connected to the second contact area, wherein the first contact finger structure and the second contact finger structure overlap in places, a current distribution layer electrically conductively connected to the first contact layer, a connection layer electrically conductively connected to the first contact layer via the current distribution layer and an insulation layer arranged in places between the connection layer and the current distribution layer, wherein the insulation layer has at least one opening.

Abstract: A method of forming a semiconductor structure is provided. Trenches are formed in a first dielectric layer having a first height on a substrate. First III-V semiconductor patterns including aluminum are formed in the trenches to a second height lower than the first height. Second III-V semiconductor patterns are formed on the first III-V semiconductor patterns to a third height not higher than the first height to form fins including the first and second III-V semiconductor patterns. The first dielectric layer is completely removed to expose the fins. Selective oxidation is performed to oxidize the first III-V semiconductor patterns to form oxidized first III-V semiconductor patterns. Fin patterning is performed. A second dielectric layer is formed to cover the fins. The second dielectric layer is recessed to a level not higher than top surfaces of the oxidized first III-V semiconductor patterns. The semiconductor structure is also provided.

Abstract: An organic light-emitting device is provided. The organic light-emitting device includes: an anode; a cathode; and an organic layer between the anode and the cathode and including an emission layer, wherein the emission layer includes a first emission layer including a first host, a second host, and a first dopant, and a second emission layer including a third host, a fourth host, and a second dopant, and the organic light-emitting device satisfies Equations 1 and 2.

Abstract: [Object] A light-emitting element includes: a semiconductor layer; a first electrode portion; a second electrode portion; a first insulating layer; and a metal layer. The semiconductor layer includes an active layer, a first-conductivity-type layer, and a second-conductivity-type layer, and has a semiconductor-layer side surface including a side surface of the active layer, a side surface of the first-conductivity-type layer, and a side surface of the second-conductivity-type layer. The first electrode portion is connected to the first-conductivity-type layer. The second electrode portion is connected to the second-conductivity-type layer. The first insulating layer is in contact at least with a part of the semiconductor-layer side surface, the part of the semiconductor-layer side surface corresponding to a part of the side surface of the active layer.

Abstract: A method of producing a semiconductor memory device includes, when three directions crossing each other are set to first, second, and third directions, respectively, laminating a plurality of first laminates and a plurality of second laminates on a semiconductor substrate in the third direction. The method further includes forming ends of the plurality of first laminates in shapes of steps extending in the first direction, and forming ends of the plurality of second laminates in shapes of steps extending in both directions of the first direction and the second direction.

Abstract: A semiconductor element is formed in a mesa portion of a semiconductor substrate. A cavity is formed in a working surface of the semiconductor substrate. The semiconductor substrate is brought in contact with a glass piece made of a glass material and having a protrusion. The glass piece and the semiconductor substrate are arranged such that the protrusion extends into the cavity. The glass piece is bonded to the semiconductor substrate. The glass piece is in-situ bonded to the semiconductor substrate by pressing the glass piece against the semiconductor substrate. During the pressing a temperature of the glass piece exceeds a glass transition temperature and the temperature and a force exerted on the glass piece are controlled to fluidify the glass material and after re-solidifying the protrusion completely fills the cavity.

Abstract: A MOS transistor includes a semiconductor substrate, a drain region and a source region in the semiconductor substrate, a channel region between the drain region and the source region, a gate electrode on the channel region, and a gate dielectric layer between the gate electrode and the semiconductor substrate. The gate dielectric layer has different thicknesses. The MOS transistor has a gate-to-source/drain breakdown voltage that is lower than a gate-to-channel breakdown voltage and a gated source/drain junction breakdown voltage.

Abstract: A semiconductor device includes a substrate, a first gate structure, a plurality of first gate spacers, a second gate structure, and a plurality of second gate spacers. The substrate has a first fin structure and a second fin structure. The first gate structure is over the first fin structure, in which the first gate structure includes a first high dielectric constant material and a first metal. A bottom surface of the first high dielectric constant material is higher than bottom surfaces of the first gate spacers. The second gate structure is narrower than the first gate structure and over the second fin structure, in which the second gate structure includes a second high dielectric constant material and a second metal. A bottom surface of the second high dielectric constant material is lower than bottom surfaces of the second gate spacers.

Abstract: The present disclosure provides a method for forming patterns in a semiconductor device. In accordance with some embodiments, the method includes providing a substrate and a patterning-target layer formed over the substrate; forming a first cut pattern in a first hard mask layer formed over the patterning-target layer; forming a second cut pattern in a second hard mask layer formed over the patterning layer, the first hard mask layer having a different etching selectivity from the second hard mask layer; selectively removing a portion of the second cut pattern in the second hard mask layer and a portion of the patterning-target layer within a first trench; and selectively removing a portion of the first cut pattern in the first hard mask layer and a portion of the patterning-target layer within a second trench.

Abstract: A flexible display panel and a manufacturing method thereof are provided. The flexible display panel includes: a base substrate, a circuit structure layer, and a via hole; the circuit structure layer is located on an upper surface of the base substrate, a protrusion in an annular shape is provided at a side of the circuit structure layer away from the base substrate, the via hole penetrates the circuit structure layer, and the protrusion surrounds the via hole.

Abstract: A photosensor device and the method of making the same are provided. In one embodiment, the device includes at least one pixel cell. The at least one pixel cell includes a substrate formed from a semiconductor material, and includes first and second photosensor regions. The first photosensor region is disposed in the substrate and includes a first dopant of a first conductivity type. The second photosensor region is disposed above the first photosensor region and includes a second dopant of a second conductivity type. The second photosensor region can have an increase in dopant concentration from an outer edge to a center portion therein.

Abstract: An array substrate and a method for manufacturing the same, a method for repairing an array substrate, and a display apparatus are provided. The array substrate includes a base substrate and pixel units above the base substrate, each pixel unit includes a light emitting device, the light emitting device includes a first electrode and a second electrode, at least one pixel unit is provided with a repair structure, the repair structure includes a first part and a second part mutually insulated, the first part and the second part are electrically coupled after being repaired, the first part is electrically coupled to the first electrode of the light emitting device in the pixel unit where the repair structure is located, the second part is electrically coupled to the first electrode of the light emitting device in any pixel unit other than the pixel unit where the repair structure is located.

Abstract: A 3D semiconductor device, including: a first level including a single crystal layer, a plurality of first transistors, and a first metal layer, forming memory control circuits; a second level overlaying the single crystal layer, and including a plurality of second transistors and a plurality of first memory cells; a third level overlaying the second level, and including a plurality of third transistors and a plurality of second memory cells; where the second transistors are aligned to the first transistors with less than 40 nm alignment error, where the memory cells include a NAND non-volatile memory type, where some of the memory control circuits can control at least one of the memory cells, and where some of the memory control circuits are designed to perform a verify read after a write pulse so to detect if the at least one of the memory cells has been successfully written.