Abstract: A semiconductor device includes a substrate, a first gate structure, a plurality of first gate spacers, a second gate structure, and a plurality of second gate spacers. The substrate has a first fin structure and a second fin structure. The first gate structure is over the first fin structure, in which the first gate structure includes a first high dielectric constant material and a first metal. A bottom surface of the first high dielectric constant material is higher than bottom surfaces of the first gate spacers. The second gate structure is narrower than the first gate structure and over the second fin structure, in which the second gate structure includes a second high dielectric constant material and a second metal. A bottom surface of the second high dielectric constant material is lower than bottom surfaces of the second gate spacers.

Abstract: The present disclosure provides a method for forming patterns in a semiconductor device. In accordance with some embodiments, the method includes providing a substrate and a patterning-target layer formed over the substrate; forming a first cut pattern in a first hard mask layer formed over the patterning-target layer; forming a second cut pattern in a second hard mask layer formed over the patterning layer, the first hard mask layer having a different etching selectivity from the second hard mask layer; selectively removing a portion of the second cut pattern in the second hard mask layer and a portion of the patterning-target layer within a first trench; and selectively removing a portion of the first cut pattern in the first hard mask layer and a portion of the patterning-target layer within a second trench.

Abstract: A flexible display panel and a manufacturing method thereof are provided. The flexible display panel includes: a base substrate, a circuit structure layer, and a via hole; the circuit structure layer is located on an upper surface of the base substrate, a protrusion in an annular shape is provided at a side of the circuit structure layer away from the base substrate, the via hole penetrates the circuit structure layer, and the protrusion surrounds the via hole.

Abstract: A photosensor device and the method of making the same are provided. In one embodiment, the device includes at least one pixel cell. The at least one pixel cell includes a substrate formed from a semiconductor material, and includes first and second photosensor regions. The first photosensor region is disposed in the substrate and includes a first dopant of a first conductivity type. The second photosensor region is disposed above the first photosensor region and includes a second dopant of a second conductivity type. The second photosensor region can have an increase in dopant concentration from an outer edge to a center portion therein.

Abstract: An array substrate and a method for manufacturing the same, a method for repairing an array substrate, and a display apparatus are provided. The array substrate includes a base substrate and pixel units above the base substrate, each pixel unit includes a light emitting device, the light emitting device includes a first electrode and a second electrode, at least one pixel unit is provided with a repair structure, the repair structure includes a first part and a second part mutually insulated, the first part and the second part are electrically coupled after being repaired, the first part is electrically coupled to the first electrode of the light emitting device in the pixel unit where the repair structure is located, the second part is electrically coupled to the first electrode of the light emitting device in any pixel unit other than the pixel unit where the repair structure is located.

Abstract: A 3D semiconductor device, including: a first level including a single crystal layer, a plurality of first transistors, and a first metal layer, forming memory control circuits; a second level overlaying the single crystal layer, and including a plurality of second transistors and a plurality of first memory cells; a third level overlaying the second level, and including a plurality of third transistors and a plurality of second memory cells; where the second transistors are aligned to the first transistors with less than 40 nm alignment error, where the memory cells include a NAND non-volatile memory type, where some of the memory control circuits can control at least one of the memory cells, and where some of the memory control circuits are designed to perform a verify read after a write pulse so to detect if the at least one of the memory cells has been successfully written.

Abstract: The invention discloses a manufacturing method for FinFET device, comprises following steps: S01: providing an SOI substrate; S02: covering a middle part of the top silicon layer by using a barrier layer, and performing a silicon ion implantation on the top silicon layer, so that the buried insulator layer under the top silicon layer not covered by the barrier layer is converted into silicon-rich silicon dioxide, wherein in the top silicon layer, the part not covered by the barrier layer is called an implanted region, and the part covered by the barrier layer is called a non-implanted region; S03: removing the barrier layer, define a fin structure in the top silicon layer, the fin structure includes a channel and a source and drain, the source and drain are located on opposite sides of the channel; and the channel in the fin structure is located in the non-implanted region of the top silicon layer, the source and drain are located in the implanted region of the top silicon layer; removing the top silicon laye

Abstract: A method of forming an array of memory cells includes forming lines of covering material that are elevationally over and along lines of spaced sense line contacts. Longitudinal orientation of the lines of covering material is used in forming lines comprising programmable material and outer electrode material that are between and along the lines of covering material. The covering material is removed over the spaced sense line contacts and the spaced sense line contacts are exposed. Access lines are formed. Sense lines are formed that are electrically coupled to the spaced sense line contacts. The sense lines are angled relative to the lines of spaced sense line contacts and relative to the access lines. Other embodiments, including structure independent of method, are disclosed.

Abstract: A method of forming surface features in a hardmask layer, including etching a first surface feature into the hardmask layer, the first surface feature having a first critical dimension, performing an ion implantation process on the first surface feature to make the first surface feature resistant to subsequent etching processes, etching a second surface feature into the hardmask layer adjacent the first surface feature, wherein the first critical dimension is preserved.

Abstract: A power semiconductor module including at least one power semiconductor chip providing a power electronics switch; and a semiconductor wafer, to which the at least one power semiconductor chip is bonded; wherein the semiconductor wafer is doped, such that it includes a field blocking region and an electrically conducting region on the field blocking region, to which electrically conducting region the at least one power semiconductor chip is bonded.

Abstract: A 3D semiconductor device, the device including: a first level including a single crystal layer and a plurality of first transistors; a first metal layer including interconnects between the plurality of first transistors, where the interconnects between the plurality of first transistors includes forming a plurality of logic gates; a plurality of second transistors atop at least a portion of the first metal layer, where at least six of the plurality of first transistors are connected in series forming at least a portion of a NAND logic structure, where the plurality of second transistors are vertically oriented transistors, and where the plurality of second transistors are at least partially directly atop of the NAND logic structure; and a second metal layer atop at least a portion of the plurality of second transistors, where the second metal layer is aligned to the first metal layer with less than 150 nm misalignment, and where at least one of the second transistors is a junction-less transistor.

Abstract: A lead frame (4) includes an inner lead (5), an outer lead (2) connected to the inner lead (5), and a power die pad (7). A power semiconductor device (9) is bonded onto the power die pad (7). A first metal thin line (11) electrically connects the inner lead (5) and the power semiconductor device (9). Sealing resin (1) seals the inner lead (5), the power die pad (7), the power semiconductor device (9), and the first metal thin line (11). The sealing resin (1) includes an insulating section (15) directly beneath the power die pad (7). A thickness of the insulating section (15) is 1 to 4 times a maximum particle diameter of inorganic particles in the sealing resin (1). A first hollow (14) is provided on an upper surface of the sealing resin (1) directly above the power die pad (7) in a region without the first metal thin line (11) and the power semiconductor device (9).

Abstract: Methods for selective deposition, and structures thereof, are provided. Material is selectively deposited on a first surface of a substrate relative to a second surface of a different material composition. A passivation layer is selectively formed from vapor phase reactants on the first surface while leaving the second surface without the passivation layer. A layer of interest is selectively deposited from vapor phase reactants on the second surface relative to the passivation layer. The first surface can be metallic while the second surface is dielectric, or the second surface is dielectric while the second surface is metallic. Accordingly, material, such as a dielectric, can be selectively deposited on either metallic or dielectric surfaces relative to the other type of surface using techniques described herein. Techniques and resultant structures are also disclosed for control of positioning and shape of layer edges relative to boundaries between underlying disparate materials.

Abstract: A highly reliable bonded structure having excellent thermal fatigue resistance characteristics and thermal stress relaxation characteristics is provided. The bonded structure of the present invention comprises a first member, a second member capable of being bonded to the first member, and a bonding part interposed between a first bond surface at the first member side and a second bond surface at the second member side to bond the first member and the second member. The bonding part has at least a bonding layer, a reinforcing layer, and an intermediate layer. The bonding layer is composed of an intermetallic compound and bonded to the first bond surface.

Abstract: A light-emitting diode (LED) substrate and a manufacturing method thereof, and a display device are provided. The LED substrate includes a receiving substrate, the receiving substrate is provided thereon with a pixel definition layer and a plurality of LED units, the pixel definition layer defines a plurality of sub-pixel regions, each of the plurality of sub-pixel regions is configured to receive at least one of the plurality of LED units, and a solder point and an auxiliary metal member are both provided in the sub-pixel region, the auxiliary metal member is provided at a periphery of the solder point, an interval is provided between the solder point and the auxiliary metal member in a plan view of the receiving substrate, and a melting point of the auxiliary metal member is higher than a melting point of the solder point.

Abstract: An integrated multilayer structure, includes a substrate film having a first side and an opposite second side. The substrate film includes electrically substantially insulating material, a circuit design including a number of electrically conductive areas of electrically conductive material on the first and/or second sides of the substrate film, and a connector including a number of electrically conductive contact elements. The connector is provided to the substrate film so that it extends to both the first and second sides of the substrate film and the number of electrically conductive contact elements connect to one or more of the conductive areas of the circuit design while being further configured to electrically couple to an external connecting element responsive to mating the external connecting element with the connector on the first or second side of or adjacent to the substrate film.

Abstract: The present disclosure provides a packaging method, including: providing a first semiconductor substrate; forming a bonding region on the first semiconductor substrate, wherein the bonding region of the first semiconductor substrate includes a first bonding metal layer and a second bonding metal layer; providing a second semiconductor substrate having a bonding region, wherein the bonding region of the second semiconductor substrate includes a third bonding layer; and bonding the first semiconductor substrate to the second semiconductor substrate by bringing the bonding region of the first semiconductor substrate in contact with the bonding region of the second semiconductor substrate; wherein the first and third bonding metal layers include copper (Cu), and the second bonding metal layer includes Tin (Sn). An associated packaging structure is also disclosed.

Abstract: According to one embodiment, a radiation detector includes a first conductive layer, a second conductive layer, and a first layer. The first layer is provided between the first conductive layer and the second conductive layer. The first layer includes a first region and a second region. The first region includes a metal complex including a first metallic element. The second region includes an organic semiconductor material. The first metallic element includes at least one selected from the group consisting of Ir, Pt, Pb, and Cu.

Abstract: A method includes depositing a first dielectric structure over a non-insulator structure, removing a portion of the first dielectric structure to form a via opening, filling the via opening with a dummy structure, depositing a second dielectric structure over the dummy structure, etching a portion of the second dielectric structure to form a trench over the dummy structure, removing the dummy structure from the via opening, and filling the trench opening and the via opening with a conductive structure, wherein the conductive structure is electrically connected to the non-insulator structure.

Abstract: A fin field effect transistor (FinFET) having a tunable tensile strain and an embodiment method of tuning tensile strain in an integrated circuit are provided. The method includes forming a source/drain region on opposing sides of a gate region in a fin, forming spacers over the fin, the spacers adjacent to the source/drain regions, depositing a dielectric between the spacers; and performing an annealing process to contract the dielectric, the dielectric contraction deforming the spacers, the spacer deformation enlarging the gate region in the fin.