Abstract: Atoms are implanted in a semiconductor region at a higher concentration in a peripheral part of the semiconductor region than in a central part of the semiconductor region. A metallic region is then formed to cover the semiconductor region. A heat treatment is the performed to form an intermetallic region from the metallic region and the semiconductor region.

Abstract: Aspects of the invention include a method of tuning an interconnect that couples a first structure that is a first integrated circuit or a first laminate structure to a second structure that is a second integrated circuit or a second laminate structure. The method includes obtaining a compression requirement for a spring in a compliant layer of the interconnect. A longer path length of the spring leads to greater compression and mechanical support. Current and signal speed requirements for the interconnect are obtained. A shorter path length of the spring leads to greater current-carrying capacity and greater signal speed. Specifications for the spring are determined based on the compression requirement and the current and signal speed requirements. Determining the specifications includes determining a number of active coils of the spring to be less than two.

Abstract: A three-dimensional ferroelectric memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, where each of the electrically conductive layers contains a transition metal element-containing conductive liner and a conductive fill material portion, a vertical semiconductor channel extending vertically through the alternating stack, a vertical stack of tubular transition metal element-containing conductive spacers laterally surrounding the vertical semiconductor channel and located at levels of the electrically conductive layers, and a ferroelectric material layer located between the vertical stack of tubular transition metal element-containing conductive spacers and the transition metal element-containing conductive liner.

Abstract: One embodiment includes: a substrate; a memory cell array that extends in a direction vertical to the substrate and includes a memory string having a plurality of series-coupled memory cells, and a selection transistor coupled to one end of the memory string; a wiring portion that includes a plurality of first conducting layers and a plurality of interlayer insulating films, the first conducting layers functioning as gate electrodes of the memory cell and the selection transistor, the interlayer insulating film being positioned between the first conducting layers in above and below directions; and a second conducting layer arranged on end portions of the plurality of first conducting layers of the selection transistor. The first conducting layers are electrically coupled in common to the second conducting layer.

Abstract: A display apparatus including: a substrate including a main display area and a sensor area, the sensor area including an auxiliary pixel and a transmission portion, wherein the main display area includes a main pixel; a sensor disposed in the sensor area and configured to transmit a signal through the substrate and the transmission portion, wherein the auxiliary pixel includes an auxiliary light-emitting device including an auxiliary cathode layer, and wherein the auxiliary cathode layer includes a plurality of layers partially overlapping each other at a first overlapping portion thereof, wherein the auxiliary cathode layer does not cover the transmission portion.

Abstract: An inorganic light emitting diode device includes: a substrate including a plurality of sub-pixels; a thin film transistor (TFT) in each of the plurality of sub-pixels, wherein the TFT has at least one inorganic layer; an encapsulation layer on an organic light emitting layer, wherein the encapsulation layer includes at least one organic encapsulation layer and at least one inorganic encapsulation layer; and an opening exposing the inorganic layer of the TFT, wherein the opening connects the at least one inorganic encapsulation layer with the inorganic layer of the TFT.

Abstract: A thin film transistor includes a gate electrode, a semiconductor layer overlapped with the gate electrode, a gate insulating layer between the gate electrode and the semiconductor layer, and a source electrode and a drain electrode electrically connected to the semiconductor layer. The semiconductor layer includes a plurality of holes. The gate insulating layer may include a plurality of recess portions at a surface of the gate insulating layer facing the semiconductor layer. A method of manufacturing the thin film transistor is provided. A thin film transistor array panel and an electronic device may include the thin film transistor.

Abstract: According to one embodiment, a method for manufacturing a semiconductor memory device includes forming a stacked body by alternately stacking an insulating film and a conductive film. The method includes forming a trench in the stacked body. The trench extends in one direction and divides the conductive film. The method includes burying a diblock copolymer in the trench. The method includes phase-separating the diblock copolymer into a plurality of first blocks and an insulative second block extending in a stacking direction of the insulating film and the conductive film. The method includes forming a plurality of holes by removing the first blocks. The method includes forming charge accumulation layers on inner surfaces of the holes. And, the method includes forming a plurality of semiconductor pillars extending in the stacking direction by burying a semiconductor material in the holes.

Abstract: Performed is a hydrogen anneal of heating a semiconductor wafer on which a thin film containing a dopant and carbon is formed to an anneal temperature in an atmosphere containing hydrogen. Subsequently, a hydrogen atmosphere in a chamber is replaced with an oxygen atmosphere, and the semiconductor wafer is preheated to a preheating temperature in the oxygen atmosphere. Performed then is a flash heating treatment of heating a surface of the semiconductor wafer to a peak temperature for less than one second. The semiconductor wafer is heated in the oxygen atmosphere, thus activation of dopant and binding of carbon in the thin film and oxygen in the atmosphere are promoted, and carbon is exhausted from the thin film to prevent hardening of the thin film. As a result, the thin film containing carbon can be easily peeled from the semiconductor wafer.

Abstract: A method of manufacturing a semiconductor device may include: forming a fin-shaped structure on a substrate; forming a supporting layer on the substrate having the fin-shaped structure formed thereon, and patterning the supporting layer into a supporting portion extending from a surface of the substrate to a surface of the fin-shaped structure and thus physically connecting them; removing a portion of the fin-shaped structure close to the substrate to form a first semiconductor layer spaced apart from the substrate; growing a second semiconductor layer with the first semiconductor layer as a seed layer; and in at least a fraction of the longitudinal extent, removing the first semiconductor layer, and cutting off the second semiconductor layer on sides of the first semiconductor layer away from the substrate and close to the substrate, respectively, so that the cut-off second semiconductor layer acts as a fin of the device.

Abstract: Provided are a display panel and a display device. The display panel includes a base substrate, drive circuits, a light-blocking layer, organic light-emitting units, and fingerprint recognition units. Via holes and imaging apertures are formed in the light-blocking layer. The via holes include first via holes in communication with the imaging apertures and second via holes. Each of the first organic light-emitting units includes a first anode, and each of the second organic light-emitting units includes a second anode. The first anode and the second anode are electrically connected to the drive circuits through the first via holes or through the second via holes. In a first direction, a distance between an edge of the first anode facing close to the imaging aperture and a center of the first via hole is smaller than a distance between an edge of the second anode and a center of the second via hole.

Abstract: A magnetic random access memory includes a memory cell including a first fixed layer, a second fixed layer, and one or more free layers disposed between the first fixed layer and the second fixed layer. The first and second fixed layers are continuous layers and commonly shared by a plurality of memory cells. The magnetic random access memory has a relatively simple structure that not only reduces magnetic interference between memory cells, but also simplifies the fabrication process and increases the integration level.

Abstract: Before a start of a treatment of a semiconductor wafer to be treated first in a lot, a dummy wafer is transported into a chamber, and an atmosphere including a helium gas having high thermal conductivity is formed. When the dummy wafer is heated with light irradiation from halogen lamps, heat transfer from the dummy wafer the temperature of which has increased occurs at an upper chamber window and a lower chamber window, with the helium gas as a heating medium. At the time when the semiconductor wafer to be treated first is transported into the chamber, the upper chamber window and the lower chamber window are heated, which makes a temperature history of all the semiconductor wafers in the lot uniform. It is thus possible to omit dummy running.

Abstract: A semiconductor device including a lower structure, an upper pattern, a stacked structure, a separation structure passing through the stacked structure, a vertical structure comprising a channel layer, wherein the stacked structure comprises a plurality of interlayer insulating layers and a plurality of gate layers, the lower structure comprises a first lower pattern and a second lower pattern of a material different from a material of the first lower pattern, the first lower pattern comprises a first portion between the second lower pattern and the channel layer, a second portion extending from the first portion to a region between the second lower pattern and the upper pattern, and a third portion extending from the first portion to a region between the second lower pattern and the substrate structure, and the first lower pattern does not extend toward a side surface of the upper pattern.

Abstract: An organic light emitting display device may include a flexible substrate, a common layer, and an encapsulation member. An undercut groove may be formed on the flexible substrate. The common layer may be disposed on the flexible substrate, may include an organic light emitting layer, and may be disconnected by the groove. The encapsulation member may be disposed on the common layer, and may cover the common layer.

Abstract: An organic light emitting display apparatus is disclosed, wherein the organic light emitting display apparatus comprises a driving thin film transistor provided on a substrate and disposed in a pixel area including a plurality of sub pixels; an organic light emitting diode electrically connected with the driving thin film transistor; and a repair portion provided at one side of the organic light emitting diode, wherein the organic light emitting diode is electrically connected with the driving thin film transistor through the repair portion.

Abstract: An array substrate includes a base substrate, a pixel definition layer, a light-emitting layer, and a plurality of auxiliary electrodes. A pixel definition layer is formed on the base substrate, and includes patterned retaining walls and a plurality of openings defined by the retaining walls. A surface of each of the retaining walls facing away from the base substrate is provided with a first groove. A light-emitting layer is formed on the retaining wall and in the plurality of openings. The light-emitting layer conformally covers respective first grooves of the retaining walls to form respective second grooves. Each of the plurality of auxiliary electrodes is formed in a respective one of the second grooves.

Abstract: Microelectronic devices, stacked microelectronic devices, and methods for manufacturing microelectronic devices are described herein. In one embodiment, a set of stacked microelectronic devices includes (a) a first microelectronic die having a first side and a second side opposite the first side, (b) a first substrate attached to the first side of the first microelectronic die and electrically coupled to the first microelectronic die, (c) a second substrate attached to the second side of the first microelectronic die, (d) a plurality of electrical couplers attached to the second substrate, (e) a third substrate coupled to the electrical couplers, and (f) a second microelectronic die attached to the third substrate. The electrical couplers are positioned such that at least some of the electrical couplers are inboard the first microelectronic die.

Abstract: Methods are disclosed herein that improve contours of trenches formed when fabricating vias and conductive lines of a multi-layer interconnect (MLI) structure. An exemplary device that can result from such methods includes a via of an MLI structure and a conductive line of the MLI structure disposed over the via. A first dielectric liner layer is disposed along sidewalls of the via and sidewalls of the conductive line. A thickness of the first dielectric liner layer is substantially the same along the sidewalls of the via. A thickness of the first dielectric liner layer increases along the sidewalls of the conductive line, such that the first dielectric liner layer has a tiger-tooth shape at each bottom corner of the conductive line. A second dielectric liner layer is disposed along the first dielectric liner layer that is disposed along the sidewalls of the via.

Abstract: A self light-emitting display device includes a substrate having a circuit board and a color filter pattern on the circuit board. The circuit board includes a driving thin-film transistor. The display device further includes a passivation film above the substrate, a color conversion pattern above the passivation film and overlapping the color filter pattern, and a light-emitting layer above the passivation film and the color conversion pattern. The light emitting layer includes a flat part and a convex part. The convex part is above the color conversion pattern and protrudes convexly relative to the flat part.