Abstract: A vertical fin field effect transistor including a doped region in a substrate, wherein the doped region has the same crystal orientation as the substrate, a first portion of a vertical fin on the doped region, wherein the first portion of the vertical fin has the same crystal orientation as the substrate and a first portion width, a second portion of the vertical fin on the first portion of the vertical fin, wherein the second portion of the vertical fin has the same crystal orientation as the first portion of the vertical fin, and the second portion of the vertical fin has a second portion width less than the first portion width, a gate structure on the second portion of the vertical fin, and a source/drain region on the top of the second portion of the vertical fin.

Abstract: In accordance with the disclosure, a method of forming a nanochannel is provided. The method includes depositing a photosensitive film stack over a substrate; forming a pattern on the film stack using interferometric lithography; depositing a plurality of silica nanoparticles to form a structure over the pattern; removing the pattern while retaining the structure formed by the plurality of silica nanoparticles, wherein the structure comprises one or more enclosed nanochannels, wherein each of the one or more nanochannels comprise one or more sidewalls and a roof; and partially sealing the roof of one or more nanochannels, wherein the roof comprises no more than one unsealed nanochannel per squared micron.

Abstract: A semiconductor device includes a plurality of unit cell transistors on a common semiconductor structure, the unit cell transistors electrically connected in parallel, and each unit cell transistor including a respective gate finger. Respective threshold voltages of first and second of the unit cell transistors differ by at least 0.1 volts and/or threshold voltages of first and second segments of a third of the unit cell transistors differ by at least 0.1 volts.

Abstract: High-voltage transistor devices with two-step field plate structures and methods of fabricating the transistor devices are provided. An example high voltage transistor device includes: a gate electrode disposed over a substrate between a source region and a drain region, a first film laterally extending from over the gate electrode to over a drift region laterally arranged between the gate electrode and the drain region, a second film laterally extending over a portion of the drift region adjacent to the drain region and away from the gate electrode, and a field plate laterally extending from over the first film to over the second film. A first thickness vertically from a top surface of the gate electrode to a bottom surface of the field plate is smaller than a second thickness vertically from a top surface of the portion of the drift region to the bottom surface of the field plate.

Abstract: A semiconductor device includes a first conductor; a first insulator thereover; a first oxide thereover; a second oxide thereover; a second conductor and a third conductor that are separate from each other thereover; a third oxide over the first insulator, the second oxide, the second conductor, and the third conductor; a second insulator thereover; a fourth conductor thereover; and a third insulator over the first insulator, the second insulator, and the fourth conductor. The second oxide includes a region where the energy of the conduction band minimum of an energy band is low and a region where the energy of the conduction band minimum of the energy band is high. The energy of the conduction band minimum of the third oxide is higher than that of the region of the second oxide where the energy of the conduction band minimum is low. Side surfaces of the first oxide and the second oxide are covered with the third oxide.

Abstract: A semiconductor light-emitting device includes: a package substrate having a mounting surface on which a first circuit pattern and a second circuit pattern are disposed; a semiconductor LED chip mounted on the mounting surface, having a first surface which faces the mounting surface and on which a first electrode and a second electrode are disposed, a second surface opposing the first surface, and side surfaces located between the first surface and the second surface, the first electrode and the second electrode being connected to the first circuit pattern and the second circuit pattern, respectively; a wavelength conversion film disposed on the second surface; and a side surface inclined portion disposed on the side surfaces of the semiconductor LED chip, providing inclined surfaces, and including a light-transmitting resin containing a wavelength conversion material.

Abstract: An electroluminescent display device can include a substrate having a display area and a pad region; a thin film transistor in the display area; first and second pads in the pad region; an insulating layer covering the thin film transistor and the first and second pads; first and second pad contact holes exposing the first and second pads, respectively; a light-emitting diode electrically connected to the thin film transistor and including first and second electrodes and a light-emitting layer interposed therebetween; and first and second auxiliary pads on the insulating layer, the first and second auxiliary pads being electrically connected to the first and second pads, respectively, in which each of the first electrode and the first and second auxiliary pads includes a first layer formed of a transparent conductive material and a second layer formed of a metallic material, and a surface length between the first and second auxiliary pads is greater than a distance between the first and second auxiliary pads.

Abstract: A method of joining a semiconductor die to a passive heat exchanger can include applying a bond enhancing agent to a semiconductor device; creating an assembly that includes a thermal interface disposed on the semiconductor device such that a first major surface of the thermal interface material is in touching relation with the bond enhancing agent on the semiconductor device, and a heat exchanger disposed in touching relation with a second major surface of the thermal interface material; and reflowing the assembly such that the thermal interface bonds the heat exchanger to the semiconductor device. Embodiments can use the ability of indium to bond to a non-metallic surface to form the thermal interface, which may be enhanced by a secondary coating on either or both joining surfaces.

Abstract: A semiconductor layer may be subjected to etching to form a trench therein. An epitaxial layer may be further formed in the trench. Here, the impurity concentration of the epitaxial layer is controlled to be lower than that of the semiconductor layer. In this manner, concentration of electrical fields in the trench is reduced. A first innovations herein provides a semiconductor device including a first semiconductor layer containing impurities of a first conductivity type, a trench provided in the first semiconductor layer on a front surface side thereof, and a second semiconductor layer provided on an inner wall of the trench, where the second semiconductor layer contains impurities of the first conductivity type at a lower concentration than the first semiconductor layer.

Abstract: A semiconductor device includes a first semiconductor pattern doped with first impurities on a substrate, a first channel pattern on the first semiconductor pattern, second semiconductor patterns doped with second impurities contacting upper edge surfaces, respectively, of the first channel pattern, and a first gate structure surrounding at least a portion of a sidewall of the first channel pattern.

Abstract: The disclosed technology is directed to a method of forming a qubit device.

Abstract: The present disclosure provides a semiconductor structure, including a first semiconductor device having a first surface and a second surface, the second surface being opposite to the first surface, a semiconductor substrate over the first surface of the first semiconductor device, and a III-V etch stop layer in contact with the second surface of the first semiconductor device. The present disclosure also provides a manufacturing method of a semiconductor structure, including providing a temporary substrate having a first surface, forming a III-V etch stop layer over the first surface, forming a first semiconductor device over the III-V etch to stop layer, and removing the temporary substrate by an etching operation and exposing a surface of the III-V etch stop layer.

Abstract: An organic light-emitting diode (OLED) package structure, and an OLED display panel and a method for manufacturing same are provided. The OLED package structure includes a packaging unit and a polarizing layer. The packaging unit includes a first packaging layer, a second packaging layer, and a protective layer. The polarizing layer includes a first sub polarizing layer and a second sub polarizing layer. The first sub polarizing layer is disposed between an OLED substrate and the first packaging layer, and the second sub polarizing layer is disposed between the first packaging layer and the second packaging layer.

Abstract: A method for producing a SiC epitaxial wafer using an apparatus including a mounting plate having a recessed accommodation portion and a satellite disposed in the recessed accommodation portion, and configured so that a SiC substrate is placed on an upper surface thereof. The method includes supplying a dopant carrier gas to an outer circumference of the SiC epitaxial wafer from between the recessed accommodation portion and the satellite.

Abstract: An active side slit and an FPC side slit each extend through a second inorganic insulating film and reach a first inorganic insulating film. The active side slit is formed between an active region and an IC chip mounted region of an EL device in plan view and also, the IC chip mounted region is sandwiched between the active side slit and the FPC side slit.

Abstract: A method of forming a memory device having magnetic tracks individually comprising a plurality of magnetic domains having domain walls, includes forming an elevationally outer substrate material of uniform chemical composition. The uniform composition material is partially etched into to form alternating regions of elevational depressions and elevational protrusions in the uniform composition material. A plurality of magnetic tracks is formed over and which angle relative to the alternating regions. Interfaces of immediately adjacent of the regions individually form a domain wall pinning site in individual of the magnetic tracks. Other methods, including memory devices independent of method, are disclosed.

Abstract: A device including an SOI substrate and an isolation structure positioned at least partially in a trench that extends through a buried insulation layer and into a semiconductor bulk substrate of the SOI substrate is disclosed. The isolation structure includes a first dielectric layer positioned in a lower portion of the trench, a first material layer positioned above the first dielectric layer, the first material layer having a material different from a material of the first dielectric layer, and a second dielectric layer positioned above the first material layer, the second dielectric layer having a material different from the material of the first material layer.

Abstract: In a fingerprint recognizable organic light-emitting diode (OLED) display panel and display device provided by the present disclosure, optical fingerprint recognition is implemented by a fingerprint recognizing sensor formed by poly-Si in a thin film transistor array of the OLED display panel. Space for disposing the fingerprint recognizing sensor is enlarged because the space occupied by the poly-Si in the thin film transistors array is narrowed by reducing the number of thin film transistors. In addition, the optical fingerprint recognizing sensors are disposed within the display panel, therefore, the display panel can implement image display and fingerprint recognition sensing at the same time. As a result, the usage experience is improved because fingerprint recognition sensing can be implemented in display area. The OLED display panel of the present disclosure can be applied in a liquid crystal display panel.

Abstract: Among other things, a method of fabricating an integrated electronic device package is described. First trace portions of an electrically conductive trace are formed on an electrically insulating layer of a package structure, and vias of the conductive trace are formed in a sacrificial layer disposed on the electrically insulating layer. The sacrificial layer is removed, and a die is placed above the electrically insulating layer. Molding material is formed around exposed surfaces of the die and exposed surfaces of the vias, and a magnetic structure is formed within the layer of molding material. Second trace portions of the electrically conductive trace are formed above the molding material and the magnetic structure. The electrically conductive trace and the magnetic structure form an inductor. The electrically conductive trace may have a coil shape surrounding the magnetic structure. The die may be positioned between portions of the inductor.

Abstract: A lead frame is provided, including one or more power terminals and one or more control terminals, wherein at least one of the control terminals is externally terminated with a press-fit contact member, and wherein at least one of the control terminals and at least one power terminals are formed from different materials. With the disclosed lead frame of the invention, lower material cross sections in the power terminals will be provided because of the better electrical conductivity when using pure copper compared to alloys with higher mechanical strengths. Also specific/different plating could be added to the individual needs of the different pin types without using masks in the plating process.