Abstract: A semiconductor device includes first and second FETs including first and second channel regions, respectively. The first and second FETs include first and second gate structures, respectively. The first and second gate structures include first and second gate dielectric layers formed over the first and second channel regions and first and second gate electrode layers formed over the first and second gate dielectric layers. The first and second gate structures are aligned along a first direction. The first gate structure and the second gate structure are separated by a separation plug made of an insulating material. The first gate electrode layer is in contact with a side wall of the separation plug.

Abstract: Wafer level proximity sensors are formed by processing a silicon substrate wafer and a silicon cap wafer separately, bonding the cap wafer to the substrate wafer, forming an interconnect structure of through-silicon vias within the substrate, and singulating the bonded wafers to yield individually packaged sensors. The wafer level proximity sensor is smaller than a conventional proximity sensor and can be manufactured using a shorter fabrication process at a lower cost. The proximity sensors are coupled to external components by a signal path that includes the through-silicon vias and a ball grid array formed on a lower surface of the silicon substrate. The design of the wafer level proximity sensor passes more light from the light emitter and more light to the light sensor.

Abstract: Embodiments of the invention are directed to a first nanosheet transistor device and a second nanosheet transistor device formed on a substrate. The first nanosheet transistor includes a first inner spacer having a first inner spacer thickness, along with a first gate dielectric having a first gate dielectric thickness. The second nanosheet transistor includes a second inner spacer having a second inner spacer thickness, along with a second gate dielectric having a second gate dielectric thickness. The first inner spacer thickness is greater than the second inner spacer thickness. The first gate dielectric thickness is greater than the second gate dielectric thickness. The first inner spacer thickness combined with the first gate dielectric thickness defines a first combined thickness. The second inner spacer thickness combined with the second gate dielectric thickness defines a second combined thickness. The first combined thickness is substantially equal to the second combined thickness.

Abstract: A method for producing a bonded SOI wafer by bonding a bond wafer and a base wafer, each being formed of a silicon single crystal, together with a silicon oxide film placed therebetween, the method including: preparing, as the base wafer, a silicon single crystal wafer whose resistivity is 100 ?·cm or more and initial interstitial oxygen concentration is 10 ppma or less; forming, on the front surface of the base wafer, a silicon oxide film by performing, on the base wafer, heat treatment in an oxidizing atmosphere at a temperature of 700° C. or higher and 1000° C. or lower for 5 hours or more; bonding the base wafer and the bond wafer together with the silicon oxide film placed therebetween; and thinning the bonded bond wafer to form an SOI layer.

Abstract: Structures with a cavity beneath semiconductor devices and methods associated with forming such substrates. A first semiconductor layer is formed on a first side of a first handle wafer. A device structure is formed that is arranged at least in part in the first semiconductor layer. After forming the device structure, the first handle wafer is thinned from a second side of the first handle wafer opposite to the first side of the first handle wafer in order to form a second semiconductor layer from the first handle wafer. After thinning the first handle wafer, a cavity is formed in the second semiconductor layer. The cavity is arranged in the second semiconductor layer beneath the device structure. A second handle wafer is attached to the second semiconductor layer to close the cavity.

Abstract: A semiconductor package includes a semiconductor chip having an active surface, on which a connection pad is disposed, and an inactive surface disposed to oppose the active surface, a heat dissipation member, disposed on the inactive surface of the semiconductor chip, having a plurality of holes and including a graphite-based material, an encapsulant covering at least a portion of each of the semiconductor chip and the heat dissipation member, and a connection member, disposed on the active surface of the semiconductor chip, including a redistribution layer electrically connected to the connection pad. 0<b<0.6a, in which “a” denotes a planar area of the heat dissipation member and “b” denotes a sum of planar areas of the plurality of holes on a plane.

Abstract: A vertical fin field effect transistor including a doped region in a substrate, wherein the doped region has the same crystal orientation as the substrate, a first portion of a vertical fin on the doped region, wherein the first portion of the vertical fin has the same crystal orientation as the substrate and a first portion width, a second portion of the vertical fin on the first portion of the vertical fin, wherein the second portion of the vertical fin has the same crystal orientation as the first portion of the vertical fin, and the second portion of the vertical fin has a second portion width less than the first portion width, a gate structure on the second portion of the vertical fin, and a source/drain region on the top of the second portion of the vertical fin.

Abstract: A power converter (100) comprising a semiconductor chip (101) with a first (101a) and a parallel second (101b) surface, and through-silicon vias (TSVs, 110). The chip embedding a high-side (HS) field-effect transistor (FET) interconnected with a low side (LS) FET. Surface (101a) includes first metallic pads (111) as inlets of the TSVs, and an attachment site for an integrated circuit (IC) chip (150). Surface (101b) includes second metallic pads (115) as outlets of the TSVs, and third metallic pads as terminals of the converter: Pad (123a) as HS FET inlet, pad (122a) as HS FET gate, pad (131a) as LS FET outlet, pad (132a) as LS FET gate, and gate (140a) as common HS FET and LS FET switch-node. Driver-and-controller IC chip 150) has the IC terminals connected to respective first pads.

Abstract: The present invention discloses a method for growing gallium nitride based on graphene and magnetron sputtered aluminum nitride, and a gallium nitride thin film. The method according to an embodiment comprises: spreading graphene over a substrate; magnetron sputtering an aluminum nitrite onto the graphene-coated substrate to obtain a substrate sputtered with aluminum nitrite; placing the substrate sputtered with aluminum nitride into a MOCVD reaction chamber and heat treating the substrate to obtain a heat treated substrate; growing an aluminum nitride transition layer on the heat treated substrate and a first and a second gallium nitride layer having different V-III ratios, respectively.

Abstract: In an embodiment, a device includes: an integrated circuit die; a through via adjacent the integrated circuit die; a molding compound encapsulating the integrated circuit die and the through via; and a redistribution structure including: a first conductive via extending through a first dielectric layer, the first conductive via electrically connected to the integrated circuit die, the first dielectric layer being over the integrated circuit die, the through via, and the molding compound; and a first conductive line over the first dielectric layer and the first conductive via, the first conductive via extending into the first conductive line.

Abstract: A display device includes a display region including light emitting elements; a first inorganic insulating layer covering the light emitting elements; a first organic insulating layer on the first inorganic insulating layer; a second organic insulating layer on the first organic insulating layer; a third organic insulating layer on the second organic insulating layer; and a second inorganic insulating layer on the third organic insulating layer. Edges of the first to third organic insulating layers are between edges of the first and second inorganic insulating layers and an edge of the display region; the edge of the second organic insulating layer is between the edge of the first organic insulating layer and the edge of the display region; and the edge of the third organic insulating layer is between the edges of the first and second inorganic insulating layers and the edge of the second organic insulating layer.

Abstract: A vertical fin field effect transistor including a doped region in a substrate, wherein the doped region has the same crystal orientation as the substrate, a first portion of a vertical fin on the doped region, wherein the first portion of the vertical fin has the same crystal orientation as the substrate and a first portion width, a second portion of the vertical fin on the first portion of the vertical fin, wherein the second portion of the vertical fin has the same crystal orientation as the first portion of the vertical fin, and the second portion of the vertical fin has a second portion width less than the first portion width, a gate structure on the second portion of the vertical fin, and a source/drain region on the top of the second portion of the vertical fin.

Abstract: A gas jetting apparatus capable of uniformly jetting, even onto a treatment-target object having a high-aspect-ratio groove, a gas into the groove. The gas jetting apparatus includes a gas jetting cell unit for jetting a gas toward a treatment-target object. The gas jetting cell unit includes a first cone-shaped member and a second cone-shaped member. A gap is formed between a side surface of a first cone shape and a side surface of the second cone-shaped member. Apex sides of the cone-shaped members face the treatment-target object.

Abstract: Disclosed is a light emitting display apparatus. The light emitting display apparatus includes a substrate including a display area including a plurality of pixel areas and a non-display area surrounding the display area, first to nth gate lines passing through the display area of the substrate, first to mth data lines passing through the display area of the substrate, first to mth pixel driving power lines passing through the display area of the substrate, a plurality of pixels provided in at least one pixel area of the substrate and connected to an adjacent gate line, an adjacent data line, and an adjacent pixel driving power line, and at least one data buffer chip provided in the display area of the substrate and connected to a corresponding data line of the first to mth data lines. Accordingly, a constant data voltage charging rate of each of the pixels is maintained regardless of a distance between a data driving circuit and each of the pixels.

Abstract: Some embodiments of the present disclosure provide a semiconductor device. The semiconductor device includes a semiconductive substrate. A donor-supply layer is over the semiconductive substrate. The donor-supply layer includes a top surface. A gate structure, a drain, and a source are over the donor-supply layer. A passivation layer covers conformably over the gate structure and the donor-supply layer. A gate electrode is over the gate structure. A field plate is disposed on the passivation layer between the gate electrode and the drain. The field plate includes a bottom edge. The gate electrode having a first edge in proximity to the field plate, the field plate comprising a second edge facing the first edge, a horizontal distance between the first edge and the second edge is in a range of from about 0.05 to about 0.5 micrometers.

Abstract: A component includes a substrate and a capacitor formed in contact with the substrate. The substrate can consist essentially of a material having a coefficient of thermal expansion of less than 10 ppm/° C. The substrate can have a surface and an opening extending downwardly therefrom. The capacitor can include at least first and second pairs of electrically conductive plates and first and second electrodes. The first and second pairs of plates can be connectable with respective first and second electric potentials. The first and second pairs of plates can extend along an inner surface of the opening, each of the plates being separated from at least one adjacent plate by a dielectric layer. The first and second electrodes can be exposed at the surface of the substrate and can be coupled to the respective first and second pairs of plates.

Abstract: A semiconductor device includes a gate structure located on a substrate; and a raised source/drain region adjacent to the gate structure. An interface is between the gate structure and the substrate. The raised source/drain region includes a stressor layer providing strain to a channel under the gate structure; and a silicide layer in the stressor layer. The silicide layer extends from a top surface of the raised source/drain region and ends below the interface by a predetermined depth. The predetermined depth allows the stressor layer to maintain the strain of the channel.

Abstract: A light-emitting element according to an embodiment comprises: a substrate; a light-emitting structure comprising a first conductive semiconductor layer, an active layer, a second conductive semiconductor layer, which are successively arranged on the substrate; and first and second electrodes, which are electrically connected to the first and second conductive semiconductor layers, respectively, wherein the first electrode comprises at least one first contact portion arranged on the first conductive semiconductor layer, which is exposed to at least a part of a first area of the light-emitting structure, and connected to the first conductive semiconductor layer, and a plurality of second contact portions connected to the first conductive semiconductor layer that is exposed in a second area, which is positioned, on a plane, closer to the inner side than the first area of the light-emitting structure, and the second electrode comprises a third contact part, which is arranged in the second area of the light-emitt

Abstract: An integrated circuit structure includes a first Inter-Layer Dielectric (ILD), a gate stack in the first ILD, a second ILD over the first ILD, a contact plug in the second ILD, and a dielectric protection layer on opposite sides of, and in contact with, the contact plug. The contact plug and the dielectric protection layer are in the second ILD. A dielectric capping layer is over and in contact with the contact plug.

Abstract: A wafer processing laminate comprising a support, a temporary adhesive material layer laminated on the support, and a wafer stacked on the temporary adhesive material layer, the wafer having a front surface on which a circuit is formed and a back surface to be processed, the temporary adhesive material layer comprising a first temporary adhesive layer composed of a thermoplastic resin layer (A) laminated on the front surface of the wafer and a second temporary adhesive layer composed of a thermosetting resin layer (B) laminated on the first temporary adhesive layer, the thermoplastic resin layer (A) being soluble in a cleaning liquid (D) after processing the wafer, the thermosetting resin layer (B) being insoluble in the cleaning liquid (D) after heat curing and capable of absorbing the cleaning liquid (D) such that the cleaning liquid (D) permeates into the layer (B).