Abstract: An array substrate includes a thin film transistor on a substrate, a color pattern on the substrate, a light blocking pattern on the thin film transistor, an organic insulation layer covering the color pattern and the light blocking pattern, a pixel electrode on the organic insulation layer, and a low-reflective pattern on the pixel electrode. An opening portion is defined in the light blocking pattern and exposes the thin film transistor. A contact hole is defined in the organic insulation layer and corresponding to the opening portion. The pixel electrode is electrically connected to the thin film transistor through the contact hole. The low-reflective pattern corresponds to the opening portion.

Abstract: A method of manufacturing a semiconductor device includes: processing a substrate by operating a processing apparatus included in a substrate processing apparatus, based on a first process setting; acquiring apparatus data of the processing apparatus when processing the substrate; generating first evaluation data of the processing apparatus based on an evaluation factor corresponding to the first process setting and the apparatus data; determining one or more recipe items executable in the processing apparatus based on the first evaluation data; and notifying the one or more recipe items.

Abstract: In a general aspect, a packaged semiconductor device can include a semiconductor device and a metal leadframe structure having a signal lead that is electrically coupled with the semiconductor device. The device can also include a molding compound encapsulating at least a portion of the metal leadframe structure. At least a portion of the signal lead can be exposed outside the molding compound. The device can further include a solder plating disposed on exposed portions of the metal leadframe structure. In the device, a flank of the signal lead can have a surface area. At first portion of the surface area of the flank can be defined by the solder plating, and a second portion of the surface area of the flank can be defined by exposed metal of the metal leadframe structure. A perimeter of a surface of the exposed metal can have at least one curved edge.

Abstract: According to one embodiment, a semiconductor device includes a first semiconductor region, a second semiconductor region, a third semiconductor region, a first electrode, a second electrode, a control electrode and an insulating film. The first semiconductor region is of a first conductivity type and includes SiC. The second semiconductor region is provided on the first semiconductor region and has a first surface. The second semiconductor region is of a second conductivity type and includes SiC. The third semiconductor region is provided on the second semiconductor region, is of the first conductivity type and includes SiC. The first and second electrodes are electrically connected to the third semiconductor region. The control electrode is provided on the second semiconductor region. The insulating film is provided between the second semiconductor region and the control electrode. The insulating film contacts the first surface and the control electrode and includes nitrogen.

Abstract: An optical module includes a carrier, a light-emitting component disposed over the carrier, an optical sensor disposed over the carrier, a housing, and a lens. The housing is disposed over the carrier and encircles the light-emitting component and the optical sensor. The housing defines a first accommodation space including a first aperture and a second aperture below the first aperture. The housing includes a first sidewall surrounding the first aperture, a second sidewall surrounding the second aperture, and a first support portion where a bottom end of the first sidewall and a top end of the second sidewall meet. The lens is located in the first aperture and is supported by the first support portion. One of the light-emitting component or the optical sensor is located in the first accommodation space.

Abstract: Methods and structures for forming epitaxial layers of semipolar III-nitride materials on patterned sapphire substrates are described. Semi-nitrogen-polar GaN may be grown from inclined c-plane facets of sapphire and coalesced to form a continuous layer of (2021) GaN over the sapphire substrate. Nitridation of the sapphire and a low-temperature GaN buffer layer is used to form semi-nitrogen-polar GaN.

Abstract: A light emitting element includes a first electrode, a second electrode overlapping the first electrode, and an emission layer between the first electrode and the second electrode. The emission layer includes a quantum well that includes a first layer and a second layer, each having a different band gap. The first layer includes magnesium, and the second layer includes zinc. The first layer and the second layer are amorphous.

Abstract: The present disclosure provides a method for forming micro-electro-mechanical-system (MEMS) devices. The method includes providing a plurality of wafers; bonding a front surface of at least a first wafer onto a front surface of a second wafer; trimming an edge of and thinning the at least first wafer after the at least first wafer is bonded onto the second wafer; and bonding a first supporting plate onto a front surface of a third wafer. The method further includes thinning a back surface of the third wafer and forming alignment marks on a thinned back surface of the third wafer; bonding a second supporting plate onto the thinned back surface of the third wafer according to the alignment marks; and removing the first supporting plate and bonding the at least first wafer onto the third wafer according to the alignment marks to form a stack structure.

Abstract: A chip package is provided. The chip package includes a substrate having conductive pads therein and adjacent to a first surface thereof. Chips are attached on a second surface opposite to the first surface of the substrate, and an encapsulation layer covers the chips. First redistribution layers are disposed between the second surface of the substrate and the encapsulation layer, and second redistribution layers are disposed on the encapsulation layer. First conductive structures and second conductive structures are disposed in the encapsulation layer. Each of first and second conductive structures respectively includes at least one bonding ball. The first conductive structures are configured to connect first and second redistribution layers, and the second conductive structures are configured to connect the second redistribution layers and the chip. A method of forming the chip package is also provided.

Abstract: A method for assembling a packaged integrated circuit for operating reliably at elevated temperatures is provided. The method includes providing an extended bond pad over an original die pad of an extracted die to create a modified extracted die. The extracted die is a fully functional semiconductor die that has been removed from a finished packaged integrated circuit. The method also includes placing the modified extracted die into a cavity of a package base and bonding a new bond wire between the extended bond pad and a lead of the package base or a downbond, and sealing a package lid to the package base and the cavity of the package.

Abstract: A light-emitting device includes a light-emitting element, and a covering layer. The light-emitting element includes a top surface, a bottom surface, a light-emitting stack between the top surface and the bottom surface, and an adhesion enhancing layer surrounding the light-emitting stack. The covering layer covers the light-emitting element and contacts the adhesion enhancing layer. Moreover, the adhesion enhancing layer includes an oxide and a thickness greater than 5 nm and less than 1000 nm.

Abstract: Devices, structures, and methods thereof for providing a Schottky or Schottky-like contact as a source region and/or a drain region of a power transistor are disclosed. A power transistor structure comprises a substrate of a first dopant polarity, a drift region formed on or within the substrate, a body region formed on or within the drift region, a gate structure formed on or within the substrate, a source region adjacent to the gate structure, a drain region formed adjacent to the gate structure. At least one of the source region and the drain region is formed from a Schottky or Schottky-like contact substantially near a surface of the substrate, comprising a silicide layer and an interfacial dopant segregation layer. The Schottky or Schottky-like contact is formed by low-temperature annealing a dopant segregation implant in the source and/or drain region.

Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes forming a conductive plug that at least partially fills a contact seam void. The contact seam void is formed in a contact that extends through an ILD layer of dielectric material overlying a device region. A metallization layer is deposited overlying the contact.

Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to multi-finger devices in multiple-gate-contacted-pitch, integrated structures and methods of manufacture. The structure includes: a first plurality of fin structures formed on a substrate having a channel surface in a {110} plane; and a second plurality of fin structures formed on the substrate with a channel surface in a {100} plane, positioned in relation to the first plurality of fin structures.

Abstract: In one aspect, a silicon-controlled rectifier (SCR) includes a Zener diode embedded in the SCR. In another aspect, a laterally diffused metal oxide semiconductor (LDMOS) includes a Zener diode embedded in the LDMOS. In a further aspect, a lateral insulated-gate bipolar transistor (IGBT) includes a Zener diode embedded in the IGBT.

Abstract: The present invention provides a multi-photon-type organic electroluminescent element including a charge generation layer using a material that is difficult to be degraded even at around normal atmospheric pressure. In an organic electroluminescent element (10) including a pair of electrodes consisting of an anode (32) and a cathode (34), a plurality of light-emitting layers (50) provided between the electrodes, and a charge generation layer (70) provided between the light-emitting layers adjacent to each other, the charge generation layer contains an ionic polymer generating at least any one of an electron and a hole.

Abstract: According to an aspect, a display device includes a display unit in which a plurality of pixels are arranged in a matrix along two directions intersecting with each other. Each of the pixels includes three sub-pixels corresponding to three of four colors including a first color, a second color, a third color, and a fourth color. An area of one sub-pixel among the three sub-pixels is larger than the area of each of the other two sub-pixels. A sub-pixel of the fourth color is one of the other two sub-pixels. Pixels each including the sub-pixel of the fourth color are not adjacent to each other in at least one of the two directions in the display unit.

Abstract: A method for making a semiconductor device is provided. Raised source and drain regions are formed with a tensile strain-inducing material, after thermal treatment to form source drain extension regions, to thereby preserve the strain-inducing material in desired substitutional states.

Abstract: An upper surface of a substrate is etched using a first single-particle film as a mask. The first single-particle film is constituted of first particles having a first particle diameter. The upper surface of the substrate is etched using a second single-particle film as a mask. The second single-particle film is constituted of second particles having a second particle diameter. The second particle diameter is different from the first particle diameter.

Abstract: A method and apparatus for manufacturing a nitrogen-doped CZTSSe layer for a solar cell is disclosed. A substrate is mounted in a vacuum chamber. A plurality of effusion cells are placed within the vacuum chamber in order to evaporate copper, zinc, tin, sulfur, and/or selenium to form elemental vapors in a region proximate the substrate. An RF-based nitrogen source delivers a nitrogen plasma in the region proximal to the substrate. The elemental vapors and the nitrogen plasma form a gas mixture in the region near the substrate, which then react at the substrate to form a CZTSSe absorber layer for a solar cell.