Abstract: An electrically erasable programmable nonvolatile memory device includes a plurality of memory cells. The memory device has architecture similar to or the same as an UV-EPROM. Erasure operating is performed by applying a negative voltage to a control gate so as to inject holes into the floating gate.

Abstract: A graphics data management system that includes control tables for quickly accessing information about the display structures to be drawn. A series of control tables and hashed indexes to graphics descriptors allow structure storage editing commands to quickly and effectively edit structure details. A hierarchical graphics data language results in a hierarchical network of structure elements and associated graphic primitive commands. The editor provides a method to preserve the hierarchy while efficiently accomplishing editing tasks. Hashing tables to the structure I.D., pick I.D., label I.D. and a chained list of execute structures are maintained to rapidly access and control those elements. Structure storage is maintained in local memory with certain portions shared with the graphics control processor.

Abstract: A data processing system for executing a sequence of instructions. The data processing system includes several processors each for executing instructions. Also included is a dispatching apparatus for dispatching each of the instructions to one of the processors. Control circuitry is included for directing the concurrent execution of the dispatched instructions in the processors irrespective of the location of the instructions in the sequence. The control circuitry includes the capability to receive an instruction interrupt signal. The control circuitry then determines which instruction generated the instruction interrupt. Upon this determination, the control circuitry resets the processors and the dispatching apparatus to the state that existed when the instruction that generated the instruction interrupt was earlier executed in order to re-execute the instruction that caused the interrupt signal in accordance with its location in the instruction sequence.

Abstract: The use of a dynamically mapped virtual memory system permits the storage of data so that each data record occupies only the physical space required for the data. Furthermore, the data storage subsystem manages the allocation of physical space on the disk drives and does not rely on the file extent defined in the count key data format. Data compaction apparatus is provided to remove the gaps contained in the stream of count key data records received from the host processor. A data compression algorithm is then used to compress the received data into a compressed format for storage on the disk drives. It is the compacted, compressed data that is finally stored on the disk drives. Furthermore, any data record received from the host processor absent data in the user data field therein is simply listed in the virtual memory map as a null field occupying no physical space on the disk drives.

Abstract: A memory controller manipulated enqueuing and dequeuing process for singly linked queues in a memory system in response to single exclusive-access write and read commands from any CPU in the associated data processing system.

Abstract: A single non-privileged instruction copies a page of data from a source virtual address in an electronic medium to a destination virtual address in the same or in a different electronic storage medium, and without the intervention of any supervisory program when each medium and the virtual addresses are previously determined. The instruction is not required to specify which medium it will use, does not require its user to know what backing medium it will access, does not require main storage (MS) to be its backing medium, and allows different types of physical addressing to be used by different media. The instruction can lock any page for use in a multi-processor (MP). No physical direction of data movement is provided within the non-privileged machine instruction, which only designates virtual direction of movement. The separation of virtual direction from physical direction is done by avoiding instruction control over selection of electronic media.

Abstract: Apparatus for temporarily disabling a translation lookaside buffer in a computer system upon the occurrence of certain predefined system conditions. Such conditions may be of a first type which have been predetermined to indicate a greater risk that two or more virtual addresses stored in the TLB will simultaneously match the incoming virtual address, and/or of a second type in which access to the TLB is not needed. An example of the first type is a reference to an unmapped segment of memory. An example of the second type is the processing of a non-memory-access instruction. The apparatus may further include failsafe circuitry to shut down the TLB if at least a given number of matches occur at any time and for any reason, the given number being greater than 1. The apparatus prevents loss of data or damage to the chip where match comparisons are performed in parallel.

Abstract: A low-power SRAM with redundant rows in each of the subarrays. Conventional redundancy logic permits defective rows to be electrically replaced by redundant rows. In addition, power supply disconnect logic permits the V.sub.DD supply voltage line for the bad row to be disconnected.

Abstract: The present invention provides an extended memory capability without requiring a much faster cache memory. This is done by providing address latches on the same chip as the cache memory and providing the most significant address bit from the address latches to be combined with the output of appropriate interface logic. The result of this combination is provided as address control signal along a path to the memory which does not require as long an access time as the rest of the addresses.

Abstract: In an address translation device (11) used in combination with a main memory (12) in translating an input virtual address into an output real address, an address translation buffer (15) is for memorizing not only a plurality of buffer virtual addresses (BVA) and a plurality of buffer real addresses (BRA) corresponding to respective buffer virtual addresses but also buffer presence bits (BP) corresponding to respective buffer real addresses to indicate presence or absence of a datum of a memory real address in the main memory in correspondence to each of the buffer real addresses. A comparison control circuit (17) compares the input virtual address with a particular one of the buffer virtual addresses, that corresponds to the input virtual address to make the address translation buffer produce, as the output real address, a particular one of the buffer real addresses, which corresponds to the particular buffer virtual address when the input virtual address coincides with the particular buffer virtual address.

Abstract: The semiconductor memory module comprises a housing of plastic or ceramic in which two chips are stacked together back-to-back. The pads of the chips are electrically connected by wire bonding to beam leads which comprise outer bond leads, generally arranged outside the housing to form the contact pins or contact leads of the module to a printed circuit board, and inner bond leads in the housing. The inner bond leads are split and spread in the area of the inner lead bond ends into upper and lower sets forming a gap for receiving and holding the stacked chips.

Abstract: A translation of a portion of a virtual page number to a portion of a physical page number in a "TLB slice." The slice translation is used to index into a physical cache memory which has virtual tags in addition to physical tags and whose addresses are physical. By comparing the virtual tag to the input virtual address page number, it can be determined whether there was a hit or a miss in the combination of the TLB slice and the cache memory. By translating only a few bits of the virtual address to a few bits of a physical address, the speed of the device is greatly enhanced. This increased speed is achieved by making the TLB slice direct-mapped and by taking advantage of its small size to build it with special hardware (either high-speed RAM (random access memory) or with latches and multiplexers). There is no separate comparison at the TLB slice output for determining a TLB slice hit.

Abstract: A method and apparatus for saving memory space in a buffer whereby the valid bit in the entry of the translation lookaside buffer for a cache memory is collapsed into one of the level bits indicating the length of the virtual address. During the lookup of the translation lookaside buffer, the virtual address in each entry is compared with the virtual address from the CPU if the level/valid bit is set, i.e. the entry is valid. If the level/valid bit is not set, then no compare takes place and the lookup continues to the next entry. The length of the virtual address to be compared is further determined by the status of the remaining level bits.

Abstract: A new and improved external memory accessing system for use in a microprocessor. The system includes a physical address cache for storing a plurality of entries including register numbers and corresponding translated external memory address locations which were used for execution of previous load instructions. The system further includes means responsive to a current load instruction for determining if the address of the register specified in the load instruction is within the physical address cache and means for conveying to the external memory, at the beginning of the execution stage of the load instruction, a previously translated external memory physical address corresponding to a specified register stored in the physical address cache. Also disclosed is a new and improved address generator for generating a new translated external memory physical address which is conveyed to the external memory and to the physical address cache for updating the physical address cache.

Abstract: In a disclosed embodiment of the address space control apparatus, each general-purpose register usable as a base register is associated with another general-purpose register in addition to an access register containing a segment table origin. When a general-purpose register is selected as a base register, the contents of its associated general-purpose register are read out and added to the segment table origin from the associated access register to provide an effective segment table origin. In a modification, the access registers are omitted, and the general-purpose register selected as a base register are used to select an entry in a register or register array containing segment table origins in respective entries. In other embodiments disclosed, general-purpose registers are used in different manners to enhance virtual address space control functions.

Abstract: An IC card including application programs and a test program for a product test wherein in order to protect a predetermined region on a memory map, during an execution of the application programs, including a portion in which a pass code for providing security regarding accessing the test program is stored against an assignment, an address restriction circuit disposed on an address bus acting to restrict the value of predetermined digit of the address to thus restrict the regions capable of being accessed.

Abstract: A microprocessor which comprises a three input adder, a two input adder, apparatus for providing the components of a virtual address to the first and second adders on a first clock period, and apparatus for providing a segment base address to the first adder on the first clock period, apparatus for determining the type of addresses generated by the adders on a second clock period and for generating an output address on the second clock period, and apparatus for determining access violations during a third clock period.

Abstract: The high speed readout circuit has an amplifier unit and an operating point setting unit and reads data from a memory sense line at high speed. The circuit further includes a unit for setting an operating point of the amplifier unit by short-circuiting the input and output terminals of the amplifier in response to a first control signal and precharging the sense line up to the operating point, and a unit for setting the sense line at a voltage slightly deviating the operating point in response to a second control signal by making use of a Miller capacitance and sensing the variations from the preset voltage during a reading process.

Abstract: A method for programming programmable EPROM elements in programmable logic arrays. Multiple programming passes are made through the array, with the programming pulses decreasing in duration on each pass.

Abstract: A nonvolatile semiconductor memory including multiple memory cells. Each memory cell comprises a FET TM having a ferroelectric insulation film and two MOS transistors T1 and T2 connected in series to the ends of the source-drain path of the FET, respectively. To write data into a memory cell, an electric field is applied in a predetermined direction between the gate and the substrate of the transistor TM. The electric field polarizes the gate insulation film of the transistor TM, which is made of ferroelectric material, in the direction, thereby writing data into the memory cell. In a data read mode, if the transistor TM is on, a current flows through the transistor TM, and the potential of a bit line to which the transistor TM is coupled decreases. In contrast, if the transistor TM is off, no currents flow through this transistor TM, and the potential of the bit line to which the transistor TM is coupled remains unchanged.