Abstract: A hierarchical memory which includes a backing store read/write memory (18) for storing first words, and a read-only memory RAM (60) for storing frequently used words. The buffer store has two parts, a cache RAM (64) and a two-word queue (62) comprised of two fetch buffers. The cache RAM is provided for storing a copy of some of the word stored in the backing store in accordance with a use algorithm. The ROM, queue buffers and cache RAM are simultaneously searched to see if the address for requested words is in either of them. If not, a fetch (76) is made of the backing store (18) and the words are written into the fetch buffers. The next time that address is presented, the fetch buffers are written into the cache and simultaneously read out to the bus. A first Y-mux (63) is provided between the ROM and the cache RAM for multiplexing the appropriate ROM columns to drive the Cache RAM bit lines directly when an internal micro-address is selected.

Abstract: A translation lookaside buffer for caching virtual addresses from a plurality of sources along with the associated physical addresses which physical addresses must be rapidly accessable and in which virtual addresses may appear simultaneously from two of the sources requiring translation into physical addresses, including a primary cache for storing a plurality of individual virtual addresses and associated physical addresses from all of the plurality of sources, apparatus for storing a single virtual address and its associated physical address from one of the plurality of sources which occurs most often each time a virtual address and an associated physical address from that one of the plurality of sources is referenced in the primary cache, and apparatus for ascertaining whether the virtual address held in the apparatus for storing a single virtual address and an associated physical address is a virtual address sought when an attempt is made to access the primary cache for a virtual address from the one of

Abstract: A power source voltage tracking circuit, for providing a given voltage which is lower than power source voltage, containing a first node for applying a power source voltage, a second node and an output line, a load connected between the first node and the output line to precharge the output line with the given voltage, elements connected between said first node and said second node to charge the second node, and elements to discharges the output line charged with the given voltage in response to the charging voltage of the second node.

Abstract: A facility is provided for locating a file in a backup memory, in which each of the components forming a hierarchical pathname identifying the file is converted into a unique identity using a minimum of bytes, and in which the location of the file in backup memory is determined as a function of each such identity rather than the component names forming the hierarchical pathname.

Abstract: A circuit for preventing false programming of unselected anti-fuses in an anti-fuse array includes a series impedance including a plurality of transistors which may be used for partial address selection connected between a source of programming voltage and a bit line.

Abstract: A semiconductor memory device having normal columns and redundant columns includes normal column decoders for designating the normal columns and redundant column decoders for designating the redundant columns so that the bits from the normal columns are combined with the bits from the redundant columns so as to provide an entire byte. The normal column decoders are to be operated simultaneously with the redundant column decoders.

Abstract: A semiconductor a semiconductor memory device including a plurality of normal blocks containing only normal memory cells without a redundant memory cell and a redundant block containing only redundant memory cells.

Abstract: A computer system operable as a virtual machine system capable of accessing multiple virtual address spaces, which has an access register translation means for translating a space identifier into an origin address of a table for address translation and a translation pair memory for storing translation pairs of the space identifiers and the associated origin addresses. In each entry of the translation pair memory, a field is provided in association with the translation pair, for storing a machine identifier of the guest virtual machine associated with the translation pair. When accessing a virtual address space, a guest virtual machine makes reference only to the associated translation pair based on the virtual machine identifier thereof.

Abstract: An improved NAND type EEPROM is disclosed, in which one selecting transistor and a plurality of memory transistors constituting one memory block are connected in series, a tunnel region for writing/erasing signal charges is isolated from a read transistor region for reading presence/absence of stored charge in each of the memory transistors. The plurality of memory transistors share one selecting transistor and the read transistor region and the selecting transistor region are isolated from each other, so that the memory block can be made small and the threshold values of the plurality of memory transistors are not influenced by the number of the memory transistors.

Abstract: A memory management arrangement facilitates interprocess data transfers by eliminating the need to construct temporary mapping tables when performing the data transfer operation. The arrangement includes the use of multiple and concurrent mapping tables in conjunction with the transmission of mapping table indentification bits with each data transfer operation.

Abstract: A method of resolving conflicts when the index values of different binary bit designators are found to be equal is provided which is implementable in a virtual memory to real memory address translation scheme and alternately in a data base environment. Binary bit designators are used, each of which consists of a first compare segment, a second index segment and a third offset segment. When two indexes are found to be identical, similar groups of bits in the first segment are considered as subsidiary indexes and are utilized in sequence until all of the bits of said first segments have been used. Each time an index operation occurs a new table entry in a new table is identified, until a group of bits from the first segments of the different binary bit designators are found to be unequal. When this occurs, comparisons of the final table entries in the final table are undertaken to determine if each stored value in each final table entry is equal to the value represented by the associated first segment.

Abstract: A MOS fuse with oxide breakdown based on a MOS cell electrically programmable by tunnel effect and storage of charges at a gate. This cell is converted into a fuse by providing for the application, when the fuse has to break down, of an intense field, greater than the oxide breakdown threshold, in the tunnel window. Thus, the breakdown is irreversible. The disclosed device can be applied notably to fuses designed for the integrated circuits of memory cards.

Abstract: Bipolar transistor memory cell and method for use in a random access memory. A pair of state elements are cross coupled so that they assume opposite states in accordance with signals applied thereto, a pair of bipolar pass transistors are connected to respective ones of the state elements for applying signals to the state elements, and current flow through the pass transistors is monitored to determine the states of the state elements.

Abstract: Methods and apparatus for optimizing prefetch caching for sets of disc drives with reverse ordered logical block mapping.

Abstract: A method for retransmitting selected data elements read from a memory. A first sequence of individually addressable data elements d.sub.1, d.sub.2, . . . , d.sub.n are read from the memory. First and second signals indicate whether each data element was read without or with, respectively, a transmission error. A second sequence of data elements d.sub.i, d.sub.i+1, . . . , d.sub.n, where d.sub.i is the first data element of the first sequence to have a transmission error is then retransmitted.

Abstract: Apparatus, and accompanying methods for use therein, for translating virtual page addresses in one address space, e.g. virtual, to page addresses in a second address space, e.g. real, and specifically for increasing the speed of such translations by translating multiple contiguous virtual page addresses upon the occurrence of a miss in a translation lookaside buffer (TLB). In response to a TLB miss, the address of each virtual page in a pre-defined block of, e.g. four, contiguous virtual pages, is separately translated through segment and/or page table lookup operations to yield corresponding page frame addresses. The virtual and corresponding page frame addresses for this block are then stored within a single TLB entry.

Abstract: A non-volatile semiconductor memory device comprises an area in which only one rewriting is possible and an area in which rewriting is possible repeatedly. A control circuit generates a high voltage from a boosting circuit and operates a writing circuit to write data in the rewritable area whose address designated by an address register/decoder. The control circuit allows writing of data into the area in which only one rewriting is possible by the writing circuit in response to an external signal. Therefore, even if the writing mode is set influenced by the unstable state of the power supply, destruction of the data in the area in which only one rewriting is possible can be prevented.

Abstract: A buffer memory device comprising memory locations for successively storing successive groups of data units, the successive groups being presented during successive phases, the data units in each group having different buffer periods which are recurrent for all groups. A modulo address generator generates, for each group of data units, a series of addresses for selected locations in a memory wherein the data units will be stored, there being logic address intervals between the successive addresses in the relevant series which correspond to the buffer periods of the respective data units. In every two successive series the memory addresses are shifted by one address interval unit with respect to each other. An efficient data occupation of the memory can thus be realized with simple addressing, since the write addresses during any phase can be used as the read addresses for already stored data units. The buffer device can be used as an interleaver or de interleaver for error correction in CD apparatus.

Abstract: A semiconductor memory device includes a memory cell array block (1; MB1 to MB16) having a first column group (area I) and a second column group (area II). The device also includes sense amplifiers (10-1, 10-2, 10-3 . . . ) provided for each column to detect and amplify a read-out voltage on associated columns. The device further includes a control circuit (20) for activating the sense amplifiers for the first column group and the sense amplifiers for the second column group at different timings to reduce peak current in sensing operation. The control circuit operates in response to a column designating signal to activate first the sense amplifiers for the column group including a column connecting thereto a selected memory cell. The column designating signal includes an externally applied column address bit. The column address bit is supplied to the device simultaneous with row address bits in an address multiplexing memory device.

Abstract: A translation look-aside buffer is implemented utilizing a four-way set associative cache memory having four lines of 16 sets each. A virtual address tag and its corresponding physical address tag, as well as a number of status bits which control the type of access permitted for a given virtual address, are stored in the translation look-aside buffer. A portion of the inputted virtual address signal is used to provide a virtual address tag and is compared to the virtual address tag in the buffer memory. When the virtual address tag comparison is achieved, the physical address tags are provided as an output from the translation look-aside buffer. Also at the same time, a fault detection circuit performs various fault detection logic on the status bits, depending on the execution cycle being performed, such as read/write cycle or user/supervisor mode.