Patents Examined by Michael Trinh
  • Patent number: 8088653
    Abstract: A TFT includes a gate electrode, an active layer, a source electrode, a drain electrode, and a buffer layer. The gate electrode is formed on the substrate; the active layer is formed on the gate electrode. The source and drain electrodes, formed on the active layer, are separated by a predetermined distance. The buffer layer is formed between the active layer and the source and drain electrodes. The buffer layer has a substantially continuously varying content ratio corresponding to a buffer layer thickness. The buffer layer is formed to suppress oxidation of the active layer, and reduce contact resistance.
    Type: Grant
    Filed: October 22, 2009
    Date of Patent: January 3, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Byoung-June Kim, Sung-Hoon Yang, Min-Seok Oh, Jae-Ho Choi, Yong-Mo Choi
  • Patent number: 8084791
    Abstract: In a non-volatile memory structure, the source/drain regions are surrounded by a nitrogen-doped region. As a result, an interface between the substrate and the charge trapping layer above the nitrogen-doped region is passivated by a plurality of nitrogen atoms. The nitrogen atoms can improve data retention, and performance of cycled non-volatile memory devices.
    Type: Grant
    Filed: November 16, 2009
    Date of Patent: December 27, 2011
    Assignee: Macronix International Co., Ltd.
    Inventor: Yen-Hao Shih
  • Patent number: 8084327
    Abstract: A method for forming a field effect transistor with an active area and a termination region surrounding the active area includes forming a well region in a first silicon region, where the well region and the first silicon region are of opposite conductivity type. Gate trenches extending through the well region and terminating within the first silicon region are formed. A recessed gate is formed in each gate trench. A dielectric cap is formed over each recessed gate. The well region is recessed between adjacent trenches to expose upper sidewalls of each dielectric cap. A blanket source implant is carried out to form a second silicon region in an upper portion of the recessed well region between every two adjacent trenches. A dielectric spacer is formed along each exposed upper sidewall of the dielectric cap, with every two adjacent dielectric spacers located between every two adjacent gate trenches forming an opening over the second silicon region.
    Type: Grant
    Filed: December 30, 2008
    Date of Patent: December 27, 2011
    Assignee: Fairchild Semiconductor Corporation
    Inventor: Steven Sapp
  • Patent number: 8080438
    Abstract: A method for forming an organic semiconductor film having a high carrier mobility is provided by having an average volatilization rate of a solvent within a prescribed range during a step of drying, at the time of applying a coating solution, which includes an organic semiconductor material and a non-halogen solvent, on a substrate. In such forming method, characteristic fluctuation in repeated use of the organic semiconductor film is suppressed, and an organic thin film transistor having an excellent film forming characteristic even on an insulator with reduced gate voltage threshold can be obtained.
    Type: Grant
    Filed: June 23, 2006
    Date of Patent: December 20, 2011
    Assignee: Konica Minolta Holdings, Inc.
    Inventors: Reiko Obuchi, Katsura Hirai, Chiyoko Takemura
  • Patent number: 8059855
    Abstract: A speaker device includes a speaker and a connecting component. The speaker has a pair of input terminals spaced apart with a first predetermined distance therebetween. The connecting component electrically couples the speaker to a printed circuit board. The connecting component has a relay-use printed circuit board and a pair of lead wires. The relay-use printed circuit includes a pair of sub-board portions and a separation portion. The sub-board portions have a pair of terminal holes. The input terminals of the speaker are disposed through the terminal holes, respectively. The separation portion is disposed between the sub-board portions to couple the sub-board portions with a second predetermined distance between the terminal holes of the sub-board portions, and selectively separate the sub-board portions when the first predetermined distance between the input terminals of the speaker is different from the second predetermined distance between the terminal holes of the sub-board portions.
    Type: Grant
    Filed: January 21, 2009
    Date of Patent: November 15, 2011
    Assignee: Funai Electric Co., Ltd.
    Inventor: Susumu Yamagami
  • Patent number: 8049226
    Abstract: A light-emitting device comprises a channel structure in the semiconductor layer for connecting an electrode and an ohmic contact layer by means of a substrate transfer process including a wafer-bonding process and a substrate-lifting-off process. The channel structure is formed in the semiconductor stack for electrically connecting the ohmic contact layer and the electrode and driving the current into the light-emitting device. Thereby, a horizontal type or a vertical type of light-emitting device has a good ohmic contact and high light efficiency.
    Type: Grant
    Filed: July 2, 2008
    Date of Patent: November 1, 2011
    Assignee: Epistar Corporation
    Inventors: Jin-Ywan Lin, Tzer-Perng Chen, Pai-Hsiang Wang, Chih-Chiang Lu
  • Patent number: 8048720
    Abstract: A method of forming a wire loop is provided. The method includes: (1) forming a first fold of wire; (2) bonding the first fold of wire to a first bonding location to form a first bond; (3) extending a length of wire, continuous with the first bond, between (a) the first bond and (b) a second bonding location; and (4) bonding a portion of the wire to the second bonding location to form a second bond.
    Type: Grant
    Filed: January 30, 2008
    Date of Patent: November 1, 2011
    Assignee: Kulicke and Soffa Industries, Inc.
    Inventors: Dodgie Reigh M. Calpito, O Dal Kwon
  • Patent number: 8044466
    Abstract: An ESD protection device comprises a substrate of a first conductive type; a transistor formed in the substrate having an input terminal of the first conductive type, a control terminal of a second conductive type, and a ground terminal of the first conductive type; and a diode formed in the substrate having a first terminal of the first conductive type and a second terminal of the second conductive type, wherein the input terminal and the second terminal are coupled to an input, and the ground terminal and the first terminal are coupled to a ground.
    Type: Grant
    Filed: January 12, 2009
    Date of Patent: October 25, 2011
    Assignee: Mediatek Inc.
    Inventors: Ding-Jeng Yu, Tao Cheng, Chao-Chih Chiu
  • Patent number: 8039386
    Abstract: A method of forming a through silicon via includes forming a via opening in a substrate using a hard mask, wherein a polymer is formed in the via opening. A first wet clean removes a first portion of the polymer and forms a first carbon containing oxide along portions of the sidewalls. A first ash process modifies the first carbon containing oxide and removes a second portion of the polymer. A first wet etch removes the modified first carbon containing oxide and a third portion of the polymer. A second ash process forms a second carbon containing oxide along at least a portion of the sidewalls. A second wet etch process removes the second carbon containing oxide and a fourth portions of the polymer. A third ash process forms a third carbon containing oxide along portions of the sidewalls and removes any remaining portions of the polymer.
    Type: Grant
    Filed: March 26, 2010
    Date of Patent: October 18, 2011
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Thuy B. Dao, Ross E. Noble, Dina H. Triyoso
  • Patent number: 8039276
    Abstract: The semiconductor device si formed by forming a first metal film over a first main surface of a semiconductor wafer having a first thinkness, performing back grinding to a second main surface of the semiconductor wafer thereby making a second thickness thinner than the first thickness and forming an insulation film pattern having a first insulation film and containing an annular insulation film pattern along the periphery of a second main surface of the semiconductor wafer over the second main surface along the periphery thereof. The second main surface of the semiconductor wafer is bonded to a pressure sensitive adhesive sheet thereby holding the device semiconductor wafer by way of the pressure sensitive adhesive sheet to a dicing frame in a state where the insulation film pattern is present.
    Type: Grant
    Filed: March 8, 2010
    Date of Patent: October 18, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Haruo Amada, Kenji Shimazawa
  • Patent number: 8034672
    Abstract: A method of producing a display device includes the steps of forming gate electrodes on a substrate so that an arrangement of a source and a drain, in a pixel row direction, of a thin-film transistor formed in each of pixels on the substrate is reversed every pixel row; forming a gate insulating film and an amorphous semiconductor thin film on the substrate in that order so as to cover the gate electrodes; crystallizing the semiconductor thin film by irradiating the semiconductor thin film with an energy beam so that a scanning direction of the energy beam is the same with respect to the arrangement of the source and the drain in the pixel row direction; and forming a light-emitting element connected to the thin-film transistor.
    Type: Grant
    Filed: February 19, 2009
    Date of Patent: October 11, 2011
    Assignee: Sony Corporation
    Inventors: Hiroshi Sagawa, Naobumi Toyomura
  • Patent number: 8034650
    Abstract: A sensor for selectively determining the presence and measuring the amount of hydrogen in the vicinity of the sensor. The sensor comprises a MEMS device coated with a nanostructured thin film of indium oxide doped tin oxide with an over layer of nanostructured barium cerate with platinum catalyst nanoparticles. Initial exposure to a UV light source, at room temperature, causes burning of organic residues present on the sensor surface and provides a clean surface for sensing hydrogen at room temperature. A giant room temperature hydrogen sensitivity is observed after making the UV source off. The hydrogen sensor of the invention can be usefully employed for the detection of hydrogen in an environment susceptible to the incursion or generation of hydrogen and may be conveniently used at room temperature.
    Type: Grant
    Filed: May 7, 2010
    Date of Patent: October 11, 2011
    Assignee: University of Central Florida Research Foundation, Inc.
    Inventors: Sudipta Seal, Satyajit V. Shukla, Lawrence Ludwig, Hyoung Cho
  • Patent number: 8034705
    Abstract: A plug comprises a first insulating interlayer, a tungsten pattern and a tungsten oxide pattern. The first insulating interlayer has a contact hole formed therethrough on a substrate. The tungsten pattern is formed in the contact hole. The tungsten pattern has a top surface lower than an upper face of the first insulating interlayer. The tungsten oxide pattern is formed in the contact hole and on the tungsten pattern. The tungsten oxide pattern has a level face.
    Type: Grant
    Filed: July 16, 2009
    Date of Patent: October 11, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Suk-Hun Choi, Chang-Ki Hong, Yoon-Ho Son, Ju-Young Jung
  • Patent number: 8034656
    Abstract: An annealing method of a zinc oxide thin film, comprises loading a substrate coated with a zinc oxide thin film into a chamber, allowing a hydrogen gas to be flowed into the chamber, fixing pressure in the chamber and annealing the zinc oxide thin film using the hydrogen gas in the chamber.
    Type: Grant
    Filed: March 3, 2009
    Date of Patent: October 11, 2011
    Assignee: Kisco
    Inventor: Seung-Yeop Myong
  • Patent number: 8030179
    Abstract: The present invention provides a semiconductor device that includes: stacked semiconductor chips, each semiconductor chip including a semiconductor substrate and a first insulating layer that is provided on side faces of the semiconductor substrate and has concavities formed on side faces thereof; first metal layers that are provided in center portions of inner side faces of the concavities; and second metal layers that are provided in the concavities and are connected to the first metal layers formed on each semiconductor chip. The present invention also provides a method of manufacturing the semiconductor device.
    Type: Grant
    Filed: September 9, 2009
    Date of Patent: October 4, 2011
    Assignee: Spansion, LLC
    Inventors: Masataka Hoshino, Junichi Kasai, Kouichi Meguro, Ryota Fukuyama, Yasuhiro Shinma, Koji Taya, Masanori Onodera, Naomi Masuda
  • Patent number: 8026165
    Abstract: A process for producing at least one air gap in a microstructure, including supplying a microstructure having at least one gap filled with a sacrificial material that decomposes starting from a temperature ?1, this gap being delimited over at least one part of its surface by a non-porous membrane, composed of a material that forms a matrix and of a pore-forming agent that decomposes at a temperature ?2<?1 by at least 20° C. and that is dispersed in this matrix, then treating the microstructure at a temperature ??2 but <?1 in order to selectively decompose the pore-forming agent, then treating the microstructure at a temperature ??1 in order to decompose the sacrificial material.
    Type: Grant
    Filed: May 1, 2009
    Date of Patent: September 27, 2011
    Assignee: Commissariat a l'Energie Atomique
    Inventor: Aziz Zenasni
  • Patent number: 8026157
    Abstract: Embodiments of the present invention generally relate to methods of forming a microcrystalline silicon layer on a substrate in a deposition chamber. In, one embodiment, the method includes flowing a processing gas into a diffuser region between a backing plate and a showerhead of the deposition chamber, flowing the processing gas through a plurality of holes in the showerhead and into a process volume between the showerhead and a substrate support in the deposition chamber, igniting a plasma in the process volume, back-flowing gas ions formed in the plasma through the plurality of holes in the showerhead and into the diffuser region, mixing the gas ions and the processing gas in the diffuser region, re-flowing the gas ions and processing gas through the plurality of holes in the showerhead and into the process volume, and depositing a microcrystalline silicon layer on the substrate.
    Type: Grant
    Filed: September 2, 2009
    Date of Patent: September 27, 2011
    Assignee: Applied Materials, Inc.
    Inventors: Xiesen Yang, Yong-Kee Chae, Shuran Sheng, Liwei Li
  • Patent number: 8026120
    Abstract: A method of manufacturing an MEMS device includes: forming a covering structure having an MEMS structure and a hollow portion, which is located on a periphery of the MEMS structure and is opened to an outside, on a substrate; and performing surface etching for the MEMS structure in a gas phase by supplying an etching gas to the periphery of the MEMS structure from the outside.
    Type: Grant
    Filed: January 8, 2010
    Date of Patent: September 27, 2011
    Assignee: Seiko Epson Corporation
    Inventors: Ryuji Kihara, Shogo Inaba
  • Patent number: 8021900
    Abstract: Methods for the production of integrated optical waveguides which have a patterned upper cladding with a defined opening to allow at least one side or at least one end of a light transmissive element to be air clad The at least one side or at least one end is, for preference, a lens structure unitary with the waveguide or a bend.
    Type: Grant
    Filed: March 29, 2007
    Date of Patent: September 20, 2011
    Assignee: RPO Pty Limited
    Inventors: Ian Andrew Maxwell, Dax Kukulj, Robert Bruce Charters
  • Patent number: 8023682
    Abstract: A portable electronic device includes a housing, a circuit board, a speaker and a spatial module. The housing includes a bottom wall and a circular wall extending from the bottom wall. The bottom wall defines a sound-emitting hole. The bottom wall and the circular wall define a receiving cavity. The circuit board is positioned on the circular wall to cover the receiving cavity and includes a first surface and an opposite second surface and defines a through hole running through the circuit board. The through hole is in communication with the receiving cavity. The speaker is electrically fixed to the first surface and received in the receiving cavity with the sound-emitting surface thereof facing the sound-emitting hole. The spatial module positioned on the second surface defines a groove in communication with the through hole.
    Type: Grant
    Filed: December 12, 2008
    Date of Patent: September 20, 2011
    Assignee: Chi Mei Communications Systems, Inc.
    Inventors: Mei-Tsu Tsao, Jia-Ren Chang, Ching-Sen Tsai