Patents Examined by Michael Trinh
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Patent number: 8184826Abstract: A speaker system includes a cabinet, at least one speaker unit fixed to the cabinet, and a gas adsorbent which is situated inside the cabinet and which is made from a porous material. The speaker unit is configured with moisture-proof component parts. In the speaker system, a tubular structure which has a tubular hollow allows ventilation between an inside and an outside of the cabinet. A resonant frequency which is determined by an acoustic impedance of the tubular structure and an acoustic impedance of the cabinet is lower than a minimum resonant frequency of an acoustic impedance of the speaker system.Type: GrantFiled: July 11, 2008Date of Patent: May 22, 2012Assignee: Panasonic CorporationInventors: Toshiyuki Matsumura, Shuji Saiki
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Patent number: 8174061Abstract: Floating-gate memory cells having a floating gate with a conductive portion and a dielectric portion facilitate increased levels of charge trapping sites within the floating gate. The conductive portion includes a continuous component providing bulk conductivity to the floating gate. The dielectric portion is discontinuous within the conductive portion and may include islands of dielectric material and/or one or more contiguous layers of dielectric material having discontinuities.Type: GrantFiled: February 3, 2009Date of Patent: May 8, 2012Assignee: Micron Technology, Inc.Inventors: Chandra Mouli, Gurtej S. Sandhu
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Patent number: 8163612Abstract: Methods and heterostructure barrier varactor (HBV) diodes optimized for application with frequency multipliers at providing outputs at submillimeter wave frequencies and above. The HBV diodes include a silicon-containing substrate, an electrode over the silicon-containing substrate, and one or more heterojunction quantum wells of alternating layers of Si and SiGe of one or more electrodes of the diode. Each SiGe quantum well preferably has a floating SiGe layer between adjacent SiGe gradients followed by adjacent Si layers, such that, a single homogeneous structure is provided characterized by having no distinct separations. The plurality of Si/SiGe heterojunction quantum wells may be symmetric or asymmetric.Type: GrantFiled: December 17, 2009Date of Patent: April 24, 2012Assignee: International Business Machines CorporationInventors: Erik M Dahlstrom, Alvin J Joseph, Robert M Rassel, David C Sheridan
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Patent number: 8163609Abstract: A method of making a semiconductor device using a semiconductor substrate includes forming a first insulating layer having a first band energy over the semiconductor substrate. A first semiconductor layer having a second band energy is formed on the first insulating layer. The first semiconductor layer is annealed to form a plurality of first charge retainer globules from the first semiconductor layer. A first protective film is formed over each charge retainer globule of the plurality of first charge retainer globules. A second semiconductor layer is formed having a third band energy over the plurality of first charge retainer globules. The second semiconductor layer is annealed to form a plurality of storage globules from the second semiconductor layer over the plurality of first charge retainer globules. A magnitude of the second band energy is between a magnitude of the first band energy and a magnitude of the third band energy.Type: GrantFiled: December 9, 2010Date of Patent: April 24, 2012Assignee: Freescale Semiconductor, Inc.Inventors: Cheong Min Hong, Sung-Taeg Kang
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Patent number: 8158469Abstract: A method of fabricating an array substrate includes forming a gate line and a gate electrode; forming a gate insulating layer, an intrinsic amorphous silicon layer, an inorganic material insulating layer and a heat transfer layer on the gate line and the gate electrode; irradiating a laser beam onto the heat transfer layer to crystallize the intrinsic amorphous silicon layer into a polycrystalline silicon layer; removing the heat transfer layer; patterning the inorganic insulating material layer using a buffered oxide etchant to form an etch-stopper corresponding to the gate electrode forming an impurity-doped amorphous silicon layer and a metal layer on the etch-stopper and the polycrystalline silicon layer; patterning the metal layer to form a data line, a source electrode and a drain electrode and forming a pixel electrode on the passivation layer.Type: GrantFiled: July 26, 2010Date of Patent: April 17, 2012Assignee: LG Display Co., Ltd.Inventors: Hong-Koo Lee, Sung-Ki Kim, Jun-Hyeon Bae, Ki-Tae Kim
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Patent number: 8158509Abstract: A method of manufacturing a semiconductor device is disclosed which comprises forming a gate structure on a major surface of a semiconductor substrate with a gate insulating film interposed therebetween, forming a first insulating film to cover top and side surfaces of the gate structure and the major surface of the semiconductor substrate, reforming portions of the first insulating film which cover the top surface of the gate structure and the major surface of the semiconductor substrate by an anisotropic plasma process using a gas not containing fluorine, and removing the reformed portions of the first insulating film.Type: GrantFiled: January 4, 2010Date of Patent: April 17, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Mitsuhiro Omura, Nobuaki Yasutake
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Patent number: 8153452Abstract: The semiconductor device is formed by forming a first metal film over a first main surface of a semiconductor wafer having a first thickness, performing back grinding to a second main surface of the semiconductor wafer thereby making a second thickness thinner than the first thickness and forming an insulation film pattern having a first insulation film and containing an annular insulation film pattern along the periphery of a second main surface of the semiconductor wafer over the second main surface along the periphery thereof. The second main surface of the semiconductor wafer is bonded to a pressure sensitive adhesive sheet thereby holding the device semiconductor wafer by way of the pressure sensitive adhesive sheet to a dicing frame in a state where the insulation film pattern is present.Type: GrantFiled: September 20, 2011Date of Patent: April 10, 2012Assignee: Renesas Electronics CorporationInventors: Haruo Amada, Kenji Shimazawa
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Patent number: 8153518Abstract: In a method for fabricating a metal interconnection of a semiconductor device, a lower interconnection and a lower insulation layer are formed over a semiconductor substrate. An etch stop layer is formed over the lower insulation layer. An upper insulation layer is formed over the etch stop layer. A first via hole is formed to expose the etch stop layer corresponding to the lower interconnection. A second via hole exposing the lower interconnection is formed by a primary etching process that selectively removes the etch stop layer exposed by the first via hole. A chemical cleaning process is performed on the second via hole, wherein polymer is formed over the surface of the lower interconnection during the chemical cleaning process. The polymer is removed from the second via hole by a secondary etching process using vaporized gas.Type: GrantFiled: December 15, 2009Date of Patent: April 10, 2012Assignee: Dongbu HiTek Co., Ltd.Inventor: Chung-Kyung Jung
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Patent number: 8143084Abstract: An image sensing device for receiving an incident light having an incident angle and photo signals formed thereby is provided. The image sensing device includes a micro prism and a micro lens for adjusting the incident angle and converging the incident light, respectively, a photo sensor for converting the photo signals into electronic signals, and an IC stacking layer for processing the electronic signals.Type: GrantFiled: January 20, 2009Date of Patent: March 27, 2012Assignees: Visera Technologies Company Ltd., OmniVision Technologies, Inc.Inventor: Hsiao-Wen Lee
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Patent number: 8133770Abstract: A silicon film is crystallized in a predetermined direction by selectively adding a metal element having a catalytic action for crystallizing an amorphous silicon and annealing. In manufacturing TFT using the crystallized silicon film, TFT provided such that the crystallization direction is roughly parallel to a current-flow between a source and a drain, and TFT provided such that the crystallization direction is roughly vertical to a current-flow between a source and a drain are manufactured. Therefore, TFT capable of conducting a high speed operation and TFT having a low leak current are formed on the same substrate.Type: GrantFiled: January 20, 2011Date of Patent: March 13, 2012Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventor: Yasuhiko Takemura
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Patent number: 8116504Abstract: An electronic device (20) includes a main board (32), a protective panel (24) defining a main bore (24a), a receiver (28) and a housing (22). The protective panel is joined to an upper portion of the housing, and the housing is joined to the main board to form a chamber receiving the receiver. The housing defines a first opening (22a) corresponding to the main bore of the protective panel. The receiver and the main bore are angled relative to each other such that the main bore is partially overlapped by the receiver to form at least one secondary bore (36) on the main bore.Type: GrantFiled: August 13, 2008Date of Patent: February 14, 2012Assignee: Chi Mei Communication Systems, Inc.Inventors: Ching-Sen Tsai, Mei-Tsu Tsao, Jia-Ren Chang
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Patent number: 8114707Abstract: A temporary substrate having an array of first solder pads is bonded to the front side of a first substrate by reflowing an array of first solder balls. The first substrate is thinned by removing the back side, and an array of second solder pads is formed on the back side surface of the first substrate. The assembly of the first substrate and the temporary substrate is diced to form a plurality of stacks, each including an assembly of a first semiconductor chip and a handle portion. A second semiconductor chip is bonded to an assembly through an array of the second solder balls. The handle portion is removed from each assembly by reflowing the array of the first solder balls, while the array of the second solder balls does not reflow. The assembly is subsequently mounted on a packaging substrate employing the array of the first solder balls.Type: GrantFiled: March 25, 2010Date of Patent: February 14, 2012Assignee: International Business Machines CorporationInventors: Mukta G. Farooq, Kevin S. Petrarca, Richard P. Volant
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Patent number: 8114735Abstract: In a method of manufacturing a non-volatile memory device, a tunnel insulating layer may be formed on a channel region of a substrate. A charge trapping layer including silicon nitride may be formed on the tunnel insulating layer to trap electrons from the channel region. A heat treatment may be performed using a first gas including nitrogen and a second gas including oxygen to remove defect sites in the charge trapping layer and to densify the charge trapping layer. A blocking layer may be formed on the heat-treated charge trapping layer, and a conductive layer may then formed on the blocking layer. The blocking layer, the conductive layer, the heat-treated charge trapping layer and the tunnel insulating layer may be patterned to form a gate structure on the channel region. Accordingly, data retention performance and/or reliability of a non-volatile memory device including the gate structure may be improved.Type: GrantFiled: September 20, 2007Date of Patent: February 14, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Hong-Suk Kim, Si-Young Choi, Ki-Hyun Hwang, Han-Mei Choi, Seung-Hwan Lee, Seung-Jae Baik, Sun-Jung Kim, Kwang-Min Park, In-Sun Yi
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Patent number: 8114684Abstract: A complementary metal oxide semiconductor (CMOS) sensor system in one embodiment includes a doped substrate, a doped central island extending downwardly within the doped substrate from an upper surface of the doped substrate, and a first doped outer island extending downwardly within the doped substrate from the upper surface of the doped substrate, the first outer island electrically isolated from the central island within an upper portion of the substrate, and electrically coupled to the central island within a lower portion of the substrate.Type: GrantFiled: March 2, 2009Date of Patent: February 14, 2012Assignee: Robert Bosch GmbHInventors: Thomas Rocznik, Christoph Lang, Sam Kavusi
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Patent number: 8114691Abstract: A semiconductor light emitting diode having a textured structure and a method of manufacturing the same are provided. The semiconductor light emitting diode includes a first semiconductor layer formed into a textured structure, an intermediate layer formed between the textured structures of the patterned first semiconductor layer, and a second semiconductor layer, an active layer, and a third semiconductor layer sequentially formed on the first semiconductor layer and the intermediate layer.Type: GrantFiled: December 4, 2009Date of Patent: February 14, 2012Assignee: Samsung LED Co., Ltd.Inventors: Jeong-wook Lee, Youn-joon Sung, Ho-sun Paek
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Patent number: 8115199Abstract: An electroluminescent device comprising: a first charge carrier injecting layer for injecting positive charge carriers; a second charge carrier injecting layer for injecting negative charge carriers; and a light-emissive layer located between the charge carrier injecting layers and comprising a mixture of: a first component for accepting positive charge carriers from the first charge carrier injecting layer; a second component for accepting negative charge carriers from the second charge carrier injecting layer; and a third, organic light-emissive component for generating light as a result of combination of charge carriers from the first and second components; at least one of the first, second and third components forming a type II semiconductor interface with another of the first, second and third components.Type: GrantFiled: October 7, 2008Date of Patent: February 14, 2012Assignee: Cambridge Display Technology Ltd.Inventors: Jeremy Henley Burroughes, Richard Henry Friend, Christopher John Bright, David John Lacey, Peter Devine
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Patent number: 8111867Abstract: An electronic device (100) having a speaker (30) located in a sealed and separate speaker enclosure is described. The electronic device includes a housing (20), a circuit board (70), a cover (60), and two connecting bodies (50). The housing includes a cavity (22) defined therein for receiving the speaker. The circuit board is electrically connected to the speaker. The cover has through holes (622) defined thereon and is disposed between the housing and the circuit board. In addition, one end of the connecting bodies connects to the speaker, and the other end of the connecting bodies is configured to resist the circuit board via the through holes to electrically connect the speaker and the circuit board.Type: GrantFiled: July 10, 2008Date of Patent: February 7, 2012Assignee: Chi Mei Communication Systems, Inc.Inventor: Chin-Hung Wu
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Patent number: 8097538Abstract: A metal member layer on a silicon member layer is patterned. A sidewall film is formed on a surface of the metal member layer. The silicon member layer is patterned to form a structure including the silicon member layer and the metal member layer, the surface of which is covered with the sidewall film. After the surface of the structure is cleaned, a water-repellent protective film is formed on the surface of the structure before the surface of the structure is dried.Type: GrantFiled: March 2, 2010Date of Patent: January 17, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Tatsuhiko Koide, Hisashi Okuchi, Hidekazu Hayashi, Hiroshi Tomita
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Patent number: 8093076Abstract: Provided are an organic light emitting apparatus for use in, for example, a flat device display, and a method of producing the apparatus. The organic light emitting apparatus has sides formed by division at ends of its substrate. Three-dimensional portions are formed on the surface of the substrate along the sides. An inorganic sealing layer is formed to extend toward the three-dimensional portions.Type: GrantFiled: November 20, 2009Date of Patent: January 10, 2012Assignee: Canon Kabushiki KaishaInventors: Takuro Yamazaki, Kohei Nagayama
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Patent number: 8094853Abstract: A speaker system includes a cabinet, a front baffle, a speaker unit, a rear baffle, and a fitting member fitted in the rear baffle. The front baffle includes a front duct segment extending backward from the rear thereof. The rear baffle includes an opening portion, a duct connecting portion, and a receiving portion having a semicircular cross section. The receiving portion extends from the opening portion to the duct connecting portion while protruding backward. The opening portion, the receiving portion, and the duct connecting portion have a groove. The receiving portion has an engagement hole. The fitting member having a semicircular cross section is formed by double molding. The frame of the member is made of relatively rigid resin and the rim thereof is made of relatively flexible resin. The frame has an engagement projection. The receiving portion and the fitting member constitute a sealed rear duct segment.Type: GrantFiled: August 19, 2008Date of Patent: January 10, 2012Assignee: Sony CorporationInventor: Hideki Seki