Abstract: A method of forming a field effect transistor comprises providing a substrate comprising a biaxially strained layer of a semiconductor material. A gate electrode is formed on the biaxially strained layer of semiconductor material. A raised source region and a raised drain region are formed adjacent the gate electrode. Ions of a dopant material are implanted into the raised source region and the raised drain region to form an extended source region and an extended drain region. Moreover, in methods of forming a field effect transistor according to embodiments of the present invention, a gate electrode can be formed in a recess of a layer of semiconductor material. Thus, a field effect transistor wherein a source side channel contact region and a drain side channel contact region located adjacent a channel region are subject to biaxial strain can be obtained.

Abstract: An apparatus for mounting a speaker module to a portable terminal is provided. The speaker module is mounted to a casing frame of the terminal using a coupling part formed outside a housing of the speaker module, so as not to leave a space between the speaker module and the casing frame in a sound output direction of the speaker module. Therefore, better speaker performance can be achieved by raising the height of the speaker module of the slim portable terminal or increasing the space for the back volume.

Abstract: A method for making a solar cell includes following steps. A silicon substrate is provided, and the silicon substrate has a first surface and a second surface opposite to the first surface. A patterned mask layer is located on the second surface, and the patterned mask layer includes a number of bar-shaped protruding structures aligned side by side. A slot is defined between each two adjacent protruding structures to expose a portion of the second surface of the silicon substrate. The exposed portion of the second surface is etched to form a protruding pair. The mask layer is removed. A doped silicon layer is located on the three-dimensional nano-structures. An upper electrode is applied on at least part of a surface of the doped silicon layer. A back electrode is placed on the first surface of the silicon substrate.

Abstract: An integrated circuit has a plurality of terminals for making electrical connection to the integrated circuit. At least one device is formed adjacent an outer edge of the integrated circuit. The device includes at least one metal conductor for forming an edge seal for protecting the integrated circuit during die singulation. The device is coupled to one or more functional circuits within the integrated circuit by routing the at least one metal conductor to the one or more functional circuits, the at least one device providing a reactance value to the one or more functional circuits for non-test operational use. The device may be formed as one or more capacitors or as one or more inductors. Various structures may be used for the capacitor and the inductor.

Abstract: A method for improving capacitance uniformity in a MIM device, mainly for the purpose of improving uniformity of a thin film within the MIM device, includes eight steps in order and step S2-step S6 may be repeated for several times as needed. According to the method for improving capacitance uniformity in a MIM device of the present invention, a certain quantity of defects in the thin film are removed by means of several times of deposition/plasma processes based on the current PECVD, and uniformity of the deposited thin film is increased, thereby improving uniformity in wet etching rate of the thin film and further improving capacitance uniformity in the MIM device.

Abstract: The invention includes methods of forming field effect transistors. In one implementation, the invention encompasses a method of forming a field effect transistor on a substrate, where the field effect transistor comprises a pair of conductively doped source/drain regions, a channel region received intermediate the pair of source/drain regions, and a transistor gate received operably proximate the channel region. Such implementation includes conducting a dopant activation anneal of the pair of source/drain regions prior to depositing material from which a conductive portion of the transistor gate is made. Other aspects and implementations are contemplated.

Abstract: A method of fabricating a semiconductor device may include: alternatively stacking dielectric layers and conductive layers on a substrate to form a stack structure, forming a first photoresist pattern on the stack structure, forming a second photoresist pattern whose thickness is reduced as the second photoresist pattern extends from the center of the stack structure towards a periphery of the stacked structure by performing a heat treatment on the first photoresist pattern, etching the stack structure through the second photoresist pattern to form a slope profile on the stack structure whose thickness is reduced as the slope profile extends from the center of the stack structure towards a periphery of the stacked structure, and forming a step-type profile on the end part of the stack structure by selectively etching the dielectric layer.

Abstract: In one embodiment, a method of forming an insulating spacer includes providing a base layer, providing an intermediate layer above an upper surface of the base layer, etching a first trench in the intermediate layer, depositing a first insulating material portion within the first trench, depositing a second insulating material portion above an upper surface of the intermediate layer, forming an upper layer above an upper surface of the second insulating material portion, etching a second trench in the upper layer, and depositing a third insulating material portion within the second trench and on the upper surface of the second insulating material portion.

Abstract: A thin film transistor, including a transparent channel pattern, a transparent gate insulating layer in contact with the channel pattern, a passivation film pattern disposed on the channel pattern, a source/drain coupled to the channel pattern through a via hole in the passivation film pattern, and a gate facing the channel pattern, the gate insulating layer interposed between the gate and the channel pattern, wherein the passivation film pattern includes at least one of polyimide, photoacryl, and spin on glass (SOG).

Abstract: A method for the formation of buried cavities within a semiconductor body envisages the steps of: providing a wafer having a bulk region made of semiconductor material; digging, in the bulk region, trenches delimiting between them walls of semiconductor material; forming a closing layer for closing the trenches in the presence of a deoxidizing atmosphere so as to englobe the deoxidizing atmosphere within the trenches; and carrying out a thermal treatment such as to cause migration of the semiconductor material of the walls and to form a buried cavity. Furthermore, before the thermal treatment is carried out, a barrier layer that is substantially impermeable to hydrogen is formed on the closing layer on top of the trenches.

Abstract: A method and apparatus are described for fabricating metal gate electrodes (85, 86) over a high-k gate dielectric layer (32) having a rare earth oxide capping layer (44) in at least the NMOS device area by treating the surface of a rare earth oxide capping layer (44) with an oxygen-free plasma process (42) to improve photoresist adhesion, forming a patterned photoresist layer (52) directly on the rare earth oxide capping layer (44), and then applying a wet etch process (62) to remove the exposed portion of the rare earth oxide capping layer (44) from the PMOS device area.

Abstract: In forming a TiN film on a base material (10) by a MOCVD method, a space between a showerhead (3) and a trapping member (5) is heated by a heater (2) up to a temperature at which TDMAT is thermally decomposed, or higher. Next, source gas containing TDMAT, and so on are emitted from the showerhead (3) into a chamber (1). As a result, the TDMAT emitted into the chamber (1) is thermally decomposed into TiN, carbon, and hydrocarbon by the heater (2) in the space between the showerhead (3) and the trapping member (5). Then, the TiN, carbon, and hydrocarbon move toward the base material (10). Then, the carbon and hydrocarbon are trapped by the trapping member (5). On the other hand, the TiN passes through the trapping member (5) without being trapped to reach the base material (10). As a result, a TiN film containing neither carbon nor hydrocarbon grows on a surface of the base material (10).

Abstract: A method for making light emitting diode is provided. The method includes following steps. A light emitting diode chip is provided, the light emitting diode includes a first semiconductor layer, an active layer and a second semiconductor layers stacked on a surface of a substrate in that order. A patterned mask layer is located on the second semiconductor layer, and the patterned mask layer includes a number of bar-shaped protruding structures aligned side by side. The second semiconductor layer is etched to form a number of three-dimensional nano-structures preform. The mask layer is removed to form a number of M-shaped three-dimensional nano-structures. The second semiconductor layer and the active layer are etched to expose a portion of the first semiconductor layer. A first electrode is electrically connected with the first semiconductor layer. A second electrode is electrically connected with the second semiconductor layer.

Abstract: A carrier substrate has a mounting location with a number of electrical connection pads on a top side and external contacts connected thereto on an underside. A metal frame encloses the connection pads of the mounting location. A MEMS chip has electrical contacts on an underside. The MEMS chip is placed on the mounting location of the carrier substrate in such a way that the MEMS chip is seated with an edge region of its underside on the metal frame. Using a flip-chip process, the electrical contacts of the MEMS chip are connected to the connection pads of the carrier substrate by means of bumps the metal frame is connected to the MEMS chip such that a closed cavity is formed between MEMS chip and carrier substrate.

Abstract: An organic electro-luminescent display and a method of fabricating the same include an organic light emitting diode, a driving transistor which drives the organic light emitting diode, and a switching transistor which controls an operation of the driving transistor, wherein active layers of the switching and driving transistors are crystallized using silicides having different densities such that the active layer of the driving transistor has a larger grain size than the active layer of the switching layer.

Abstract: A method for making light emitting diode is provided. The method includes following steps. A light emitting diode chip is provided, wherein the light emitting diode chip comprises a first semiconductor layer, an active layer and a second semiconductor layers stacked together in that order. A patterned mask layer is located on a surface of the first semiconductor layer, wherein the patterned mask layer includes a number of bar-shaped protruding structures aligned side by side, and a slot is defined between each two adjacent protruding structures to expose a portion of the first semiconductor layer. The exposed portion of the first semiconductor layer is etched to form a protruding pair. A number of M-shaped three-dimensional nano-structures are formed by removing the mask layer. A first electrode is electrically connected with the first semiconductor layer. A second electrode is electrically connected with the second semiconductor layer.

Abstract: A method for depositing a layer of phosphor-containing material on a plurality of LED dies includes disposing a template with a plurality of openings on an adhesive tape and disposing each of a plurality of LED dies in one of the plurality of openings of the template. The method also includes forming a patterned dry film photoresist layer over the template and the plurality of LED dies. The photoresist layer has a plurality of openings configured to expose a top surface of each of the LED dies. Next, a phosphor-containing material is disposed on the exposed top surface of each the LED dies. The method further includes removing the photoresist layer and the template.

Abstract: An expansion/contraction measuring apparatus includes a transport section which transports a flexible substrate along a surface of the substrate; a detecting section detecting first and second marks which are formed on the substrate while being separated from each other by a predetermined spacing distance in a transport direction of the substrate and which are moved, in accordance with the transport of the substrate, to first and second detection areas disposed on a transport route for the substrate respectively; a substrate length setting section which sets a length of the substrate along the transport route between the first and second detection areas to a reference length; and a deriving section which derives information about expansion/contraction of the substrate in relation to the transport direction based on a detection result of the first and second marks. Accordingly, the expansion/contraction state of an expandable/contractible substrate is measured highly accurately.

Abstract: An insulated-gate field-effect transistor (100, 100V, 140, 150, 150V, 160, 170, 170V, 180, 180V, 190, 210, 210W, 220, 220U, 220V, 220W, 380, or 480) has a hypoabrupt vertical dopant profile below one (104 or 264) of its source/drain zones for reducing the parasitic capacitance along the pn junction between that source/drain zone and adjoining body material (108 or 268). In particular, the concentration of semiconductor dopant which defines the conductivity type of the body material increases by at least a factor of 10 in moving from that source/drain zone down to an underlying body-material location no more than 10 times deeper below the upper semiconductor surface than that source/drain zone. The body material preferably includes a more heavily doped pocket portion (120 or 280) situated along the other source/drain zone (102 or 262).

Abstract: A method of manufacture of an integrated circuit packaging system includes: fabricating a base package substrate; coupling a conductive column lead frame to the base package substrate by: providing a lead frame support, patterning a conductive material on the lead frame support including forming an interconnect securing structure, and coupling the conductive material to the base package substrate; forming a base package body between the base package substrate and the conductive column lead frame; and removing the lead frame support from the conductive column lead frame for exposing the interconnect securing structure from the base package body.