Patents Examined by Michael Trinh
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Patent number: 8278205Abstract: The present invention is a method for manufacturing a semiconductor device having a conductor and an insulating film on a substrate, the method including the steps of forming the conductor on the substrate, forming the insulating film on the conductor, removing the insulating film on the conductor, and blowing an organosilane gas and a hydrogen gas to reduce an oxidized region on the conductor, wherein the oxidized region on the conductor is formed when the insulating film is removed.Type: GrantFiled: February 25, 2009Date of Patent: October 2, 2012Assignee: Tokyo Electron LimitedInventor: Takaaki Matsuoka
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Patent number: 8278144Abstract: A solder mask for flip chip interconnection has a common opening that spans a plurality of circuit elements. The solder mask allows confinement of the solder during the remelt stage of interconnection, yet it is within common design rules for solder mask patterning. Also, a substrate for flip chip interconnection includes a substrate having the common opening that spans a plurality of circuit elements. Also, a flip chip package includes a substrate having a common opening that spans a plurality of circuit elements.Type: GrantFiled: January 30, 2009Date of Patent: October 2, 2012Assignee: STATS ChipPAC, Ltd.Inventor: Rajendra D. Pendse
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Patent number: 8273613Abstract: There is provided a method by which lightly doped drain (LDD) regions can be formed easily and at good yields in source/drain regions in thin film transistors possessing gate electrodes covered with an oxide covering. A lightly doped drain (LDD) region is formed by introducing an impurity into an island-shaped silicon film in a self-aligning manner, with a gate electrode serving as a mask. First, low-concentration impurity regions are formed in the island-shaped silicon film by using rotation-tilt ion implantation to effect ion doping from an oblique direction relative to the substrate. Low-concentration impurity regions are also formed below the gate electrode at this time. After that, an impurity at a high concentration is introduced normally to the substrate, so forming high-concentration impurity regions. In the above process, a low-concentration impurity region remains below the gate electrode and constitutes a lightly doped drain region.Type: GrantFiled: November 19, 2009Date of Patent: September 25, 2012Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Hongyong Zhang, Yasuhiko Takemura, Toshimitsu Konuma, Hideto Ohnuma, Naoaki Yamaguchi, Hideomi Suzawa, Hideki Uochi
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Patent number: 8265319Abstract: Speaker assemblies for portable media players are disclosed herein. Speaker assemblies can include means for contracting and expanding the speakers to facilitate viewing and listening to a PMP in multiple orientations. Preferred means for contracting and expanding the speaker casings are operably coupled with means for rotating the PMP, such that when the PMP is in a wide viewable configuration, the speakers are expanded.Type: GrantFiled: September 24, 2007Date of Patent: September 11, 2012Assignee: Zipbuds, LLCInventors: Erik Groset, Robin Michael Defay
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Patent number: 8265329Abstract: Improved approaches for providing a speaker within a housing of a portable electronic device are disclosed. The housing of the portable electronic device can be compact, such as a low profile housing. In one embodiment, an acoustic chamber for a speaker can be formed internal to a housing for a portable electronic device using non-dedicated space. In another embodiment, irregular surfaces can be sealed so that an acoustic chamber for a speaker can be formed internal to a housing for a portable electronic device.Type: GrantFiled: September 29, 2008Date of Patent: September 11, 2012Assignee: Apple Inc.Inventors: Gloria Lin, Derek B. Barrentine, Michael Rosenblatt
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Patent number: 8258426Abstract: Embodiments of the present invention generally provide methods and apparatus for material removal using lasers in the fabrication of solar cells. In one embodiment, an apparatus is provided that precisely removes portions of a dielectric layer deposited on a solar cell substrate according to a desired pattern and deposits a conductive layer over the patterned dielectric layer. In one embodiment, the apparatus also removes portions of the conductive layer in a desired pattern. In certain embodiments, methods for removing a portion of a material via a laser without damaging the underlying substrate are provided. In one embodiment, the intensity profile of the beam is adjusted so that the difference between the maximum and minimum intensity within a spot formed on a substrate surface is reduced to an optimum range. In one example, the substrate is positioned such that the peak intensity at the center versus the periphery of the substrate is lowered.Type: GrantFiled: August 21, 2009Date of Patent: September 4, 2012Assignee: Applied Materials, Inc.Inventors: Zhenhua Zhang, Virendra V. S. Rana, Vinay K. Shah, Chris Eberspacher
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Patent number: 8247312Abstract: A method of printing an ink on a wafer surface configured with a set of non-rounded peaks and a set of non-rounded valleys is disclosed. The method includes exposing the wafer including at least some non-rounded peaks and at least some of the non-rounded valleys in a region to an etchant. The method further includes depositing the ink on the region, wherein a set of rounded peaks and a set of rounded valleys are formed.Type: GrantFiled: April 24, 2008Date of Patent: August 21, 2012Assignee: Innovalight, Inc.Inventors: Malcolm Abbott, Maxim Kelman, Karel Vanheusden
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Patent number: 8236681Abstract: In a formation process of a semi-global interconnect in a Cu damascene multilayer wiring structure, it is the common practice, upon formation of the damascene wiring structure, to remove an etch stop insulating film from a via bottom by dry etching and then carry out nitrogen plasma treatment to reduce carbon deposits on the surface of the via bottom. Study by the present inventors has revealed that when a sequence of successive discharging for the removal of electrostatic charge by using nitrogen plasma and transportation of the wafer is performed, a Cu hollow is generated on the via bottom at the end of the via chain coupled to a pad lead interconnect having a length not less than a threshold value.Type: GrantFiled: March 3, 2010Date of Patent: August 7, 2012Assignee: Renesas Electronics CorporationInventor: Makoto Nagano
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Patent number: 8236647Abstract: Provided is a method for fabricating a nonvolatile memory device capable of improving charge retention characteristics. The method for fabricating a nonvolatile memory device includes forming a charge trapping layer with a memory region and a charge blocking region on a semiconductor substrate, and trapping charges in the charge blocking region of the charge trapping layer.Type: GrantFiled: August 4, 2009Date of Patent: August 7, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Juyul Lee, Seungjae Baik, Kihyun Hwang, Siyoung Choi
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Patent number: 8236682Abstract: Provided is a method of forming a contact structure. The method includes forming a conductive pattern on a substrate. An interlayer insulating layer covering the conductive pattern is formed. The interlayer insulating layer is patterned to form an opening partially exposing the conductive pattern. An oxide layer is formed on substantially the entire surface of the substrate on which the opening is formed. A reduction process is performed to reduce the oxide layer. Here, the oxide layer on a bottom region of the opening is reduced to a catalyst layer, and the oxide layer on a region other than the bottom region of the opening is reduced to a non-catalyst layer. A nano material is grown from the catalyst layer, so that a contact plug is formed in the opening.Type: GrantFiled: March 30, 2010Date of Patent: August 7, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Kyung-Rae Byun, Suk-Ho Joo, Min-Joon Park
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Patent number: 8222071Abstract: A method for making a memory cell assembly includes forming a memory cell access layer over a substrate to create an access device with a bottom electrode. A memory material layer is formed over the memory cell access layer in electrical contact with the bottom electrode. A first electrically conductive layer is formed over the memory material layer. A first mask, extending in a first direction, is formed over the first electrically conductive layer and then trimmed so that those portions of the first electrically conductive layer and the memory material layer not covered by the first mask are removed.Type: GrantFiled: March 17, 2011Date of Patent: July 17, 2012Assignee: Macronix International Co., Ltd.Inventor: Hsiang-Lan Lung
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Patent number: 8222080Abstract: Provided is a fabrication method of a package structure, including cutting a full-panel packaging substrate into a plurality of packaging substrate blocks, each of which has a plurality of packaging substrate units; mounting and packaging a semiconductor chip on each of the packaging substrate units and securing and protecting the semiconductor chips with an encapsulating material, thereby forming a plurality of packaging substrate blocks with packaging substrate units; and cutting the packaging substrate blocks to separate the packaging substrate units from each other.Type: GrantFiled: August 30, 2010Date of Patent: July 17, 2012Assignee: Unimicron Technology CorporationInventor: Chu-Chin Hu
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Patent number: 8207059Abstract: A layer of a porous insulating film precursor is formed on or over a substrate, a layer of a specific silicon compound is then formed, this silicon compound layer is pre-cured as necessary, and the porous insulating film precursor is exposed to UV through the silicon compound layer or pre-cured layer.Type: GrantFiled: August 4, 2008Date of Patent: June 26, 2012Assignee: Fujitsu LimitedInventors: Shirou Ozaki, Yoshihiro Nakata, Ei Yano
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Patent number: 8202741Abstract: A compliant bonding structure is disposed between a semiconductor device and a mount. In some embodiments, the device is a light emitting device. When the semiconductor light emitting device is attached to the mount, for example by providing ultrasonic energy to the semiconductor light emitting device, the compliant bonding structure collapses to partially fill a space between the semiconductor light emitting device and the mount. In some embodiments, the compliant bonding structure is plurality of metal bumps that undergo plastic deformation during bonding. In some embodiments, the compliant bonding structure is a porous metal layer.Type: GrantFiled: March 4, 2009Date of Patent: June 19, 2012Assignees: Koninklijke Philips Electronics N.V., Philips Lumileds Lighting Company, LLCInventors: James G. Neff, John E. Epler, Stefano Schiaffino
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Patent number: 8204245Abstract: A sound projecting bumper may include a vehicle bumper configured to be attached to a vehicle, the bumper comprising a plurality of uprights and at least one generally horizontal member, the bumper further comprising a horn for emitting sound, the horn comprising a driver, a cone, a speaker and a diaphragm for producing the sound, and wiring to connect the bumper device to the vehicle's electrical system. The horn may be configured to focus sound particularly forward of the vehicle. The driver may be attached to one of the uprights, and the bumper may include a second driver attached to a second one of the uprights. The horn may be generally aligned with one of the uprights, or the horn may be formed in a generally horizontal member. The bumper may further include a channel in the generally horizontal member, wherein the channel extends generally along a portion of the generally horizontal member, turning to form the horn.Type: GrantFiled: October 31, 2008Date of Patent: June 19, 2012Assignee: Lund Industries, Inc.Inventors: Michael W. Tobin, Paul A. Lundberg
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Patent number: 8198110Abstract: This invention is related to a thin film transistor (TFT) array and method of making same, for use in an active matrix liquid crystal display (AMLCD) having a high pixel aperture ratio. The TFT array and corresponding display are made by forming the TFTs and corresponding address lines on a substrate, coating the address lines and TFTs with a photo-imageable insulating layer which acts as a negative resist, exposing portions of the insulating layer with UV light which are to remain on the substrate, removing non-exposed areas of the insulating layer so as to form contact vias, and depositing pixel electrodes on the substrate over the insulating layer so that the pixel electrodes contact respective TFT source electrodes through the contact vias. The resulting display has an increased pixel aperture ratio because the pixel electrodes are formed over the insulating layer so as to overlap portions of the array address lines.Type: GrantFiled: October 14, 2008Date of Patent: June 12, 2012Assignee: LG Display Co., Ltd.Inventors: Willem Den Boer, John Z. Z. Zhong, Tieer Gu
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Patent number: 8198150Abstract: A low thermal pathway is provided from the top surface of a silicon substrate to the bottom surface of the silicon substrate by first forming aluminum plugs in the bottom surface of the silicon substrate that contact the silicon substrate and extend up towards the top surface, and then heating the aluminum plugs to a temperature for a period of time sufficient to cause spikes to grow from the sides of the aluminum plugs.Type: GrantFiled: December 3, 2009Date of Patent: June 12, 2012Assignee: National Semiconductor CorporationInventor: Visvamohan Yegnashankaran
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Patent number: 8193051Abstract: The present invention provides a semiconductor structure including a semiconductor substrate having a plurality of source and drain diffusion regions located therein, each pair of source and drain diffusion regions are separated by a device channel. The structure further includes a first gate stack of pFET device located on top of some of the device channels, the first gate stack including a high-k gate dielectric, an insulating interlayer abutting the gate dielectric and a fully silicided metal gate electrode abutting the insulating interlayer, the insulating interlayer includes an insulating metal nitride that stabilizes threshold voltage and flatband voltage of the p-FET device to a targeted value and is one of aluminum oxynitride, boron nitride, boron oxynitride, gallium nitride, gallium oxynitride, indium nitride and indium oxynitride.Type: GrantFiled: March 14, 2011Date of Patent: June 5, 2012Assignee: International Business Machines CorporationInventors: Nestor A. Bojarczuk, Jr., Cyril Cabral, Jr., Eduard A. Cartier, Matthew W. Copel, Martin M. Frank, Evgeni P. Gousev, Supratik Guha, Rajarao Jammy, Vijay Narayanan, Vamsi K. Paruchuri
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Patent number: 8187914Abstract: Provided are methods of forming a phase change memory device. A semiconductor device having a lower electrode and an interlayer insulating layer may be prepared. The lower electrode may be surrounded by the interlayer insulating layer. Source gases, a reaction gas and a purge gas may be injected into a process chamber of a semiconductor fabrication device to form a phase change material layer on a semiconductor substrate. The source gases may be simultaneously injected into the process chamber. The phase change material layer may be in contact with the lower electrode through the interlayer insulating layer. The phase change material layer may be etched to form a phase change memory cell in the interlayer insulating layer. An upper electrode may be formed on the phase change memory cell.Type: GrantFiled: March 25, 2010Date of Patent: May 29, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Jin-Il Lee, Urazaev Vladimir, Jin-Ha Jeong, Seung-Back Shin, Sung-Lae Cho, Hyeong-Geun An, Dong-Hyun Im, Young-Lim Park, Jung-Hyeon Kim
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Patent number: 8189848Abstract: A speaker module for a portable terminal is provided. The speaker module includes an upper case constituting a part of a module housing, a speaker unit, including a magnetic body, a voice coil and a vibration plate, formed in the upper case and a vibration motor, which is installed in the upper case and on one side of the speaker unit. The speaker module as structured above can secure a sufficient sound pressure and a sound volume in a portable terminal having a slim construction, makes it easier to secure space for installation within a portable terminal having a small size and slim construction in such a manner that a vibration motor, etc. are received and integrated in a module housing, and can improve the quality of sound in a portable terminal by achieving improved smoothness of output sound pressure in an audio frequency range.Type: GrantFiled: May 30, 2008Date of Patent: May 29, 2012Assignee: Samsung Electronics Co., Ltd.Inventor: Ho-Yeong Lim