Abstract: A micro electro mechanical system (MEMS) structure is provided, which includes a first substrate, a second substrate, a MEMS device and a hydrophobic semiconductor layer. The first substrate has a first portion. The second substrate is substantially parallel to the first substrate and has a second portion substantially aligned with the first portion. The MEMS device is between the first portion and the second portion. The hydrophobic semiconductor layer is made of germanium (Ge), silicon (Si) or a combination thereof on the first portion, the second portion or the first portion and the second portion and faces toward the MEMS device. A cap substrate for a MEMS device and a method of fabricating the same are also provided.

Abstract: A semiconductor device includes a gate disposed over a substrate; a source region and a drain region on opposing sides of the gate; and a pair of trench contacts over and abutting an interfacial layer portion of at least one of the source region and the drain region; wherein the interfacial layer includes boron in an amount in a range from about 5×1021 to about 5×1022 atoms/cm2.

Abstract: Provided is a CIGSSe thin film for a solar cell, a method for preparing the same, and a solar cell using the same. More particularly, the CIGSSe thin film for a solar cell shows a decrease in peak intensity of sulfur from the surface of the thin film to the local minimum value point of sulfur content in the depth direction, after the analysis based on the Auger electron spectroscopy, and thus controls the band-gap in the thin film. Therefore, the solar cell including the CIGSSe thin film shows an excellent effect in improving photoelectric conversion efficiency.

Abstract: Mechanisms are provided for sacrificial carrier dicing of semiconductor wafers. A bottom layer of a semiconductor wafer is bonded to a top layer of a sacrificial carrier. The semiconductor wafer is diced into a set of chips, such that the dicing cuts through the semiconductor wafer and into the sacrificial carrier and such that the sacrificial carrier dresses a diamond blade of a saw so as to expose one or more new, sharp layers of diamonds on the diamond blade.

Abstract: A III-nitride semiconductor device which includes a barrier body between the gate electrode and the gate dielectric thereof.

Abstract: One method disclosed includes, among other things, forming an overall fin structure having a stepped cross-sectional profile, the fin structure having an upper part and a lower part positioned under the upper part, wherein the upper part has a first width and the lower part has a second width that is less than the first width, forming a layer of insulating material in trenches adjacent the overall fin structure such that the upper part of the overall fin structure and a portion of the lower part of the overall fin structure are exposed above an upper surface of the layer of insulating material, and forming a gate structure around the exposed upper part of the overall fin structure and the exposed portion of the lower part of the overall fin structure.

Abstract: An integrated circuit may be formed by forming an isolation recess in a single-crystal silicon-based substrate. Sidewall insulators are formed on sidewalls of the isolation recess. Thermal oxide is formed at a bottom surface of the isolation recess to provide a buried isolation layer, which does not extend up the sidewall insulators. A single-crystal silicon-based semiconductor layer is formed over the buried isolation layer and planarized to be substantially coplanar with the substrate adjacent to the isolation recess, thus forming an isolated semiconductor layer over the buried isolation layer. The isolated semiconductor layer is laterally separated from the substrate.

Abstract: An integrated circuit is formed by forming an isolation recess in a single crystal substrate which includes silicon, filling the isolation recess with isolation dielectric material, and planarizing the isolation dielectric material to be coplanar with the top surface of the substrate to form a buried isolation layer. A non-selective epitaxial process forms single-crystalline silicon-based semiconductor material on exposed areas of the substrate and polycrystalline or amorphous silicon-based material on the buried isolation layer. A cap layer is formed over the epitaxial silicon-based material, and a radiantly-induced recrystallization process causes the polycrystalline or amorphous silicon-based material to form single-crystalline semiconductor over the buried isolation layer.

Abstract: A film deposition apparatus includes a turntable to rotate a substrate thereon, a process gas supply part to supply a process gas to form a thin film on the substrate, a heating part to heat the substrate up to a predetermined film deposition temperature to form a thin film, a plasma treatment part to treat the thin film for modification, a heat lamp provided above the turntable and configured to heat the substrate up to a temperature higher than the predetermined film deposition temperature by irradiating the substrate with light in an adsorption wavelength range of the substrate, and a control part to output a control signal so as to repeat a step of depositing the thin film and a step of modifying the thin film by the plasma, and then to stop supplying the process gas and to heat the substrate by the heat lamp.

Abstract: A method of improving chip-to-chip alignment accuracy for circuitry-including wafer-to-wafer bonding. The method comprises providing separate stages for holding first and second circuitry-including wafers, each stage including a plurality of adjacent thermal actuators arranged in an array integrated with the stage; determining planar distortions of a bonding surface of the first and second circuitry-including wafers; mapping the planar distortions for each wafer based on the relative planar distortions thereon; deducing necessary local thermal expansion measurements for each wafer to compensate for the relative distortions based on the mapping; translating the thermal expansion measurements into a non-uniform wafer temperature profile model and a local heat flux profile model for each wafer; aligning the first and second wafers; and bonding the first and second wafers together.

Abstract: A method for manufacturing a MOS transistor device includes following steps. A substrate including at least an isolation structure formed therein is provided. Next, a MOS transistor device is formed on the substrate, the MOS transistor device includes a gate, a source region, a drain region and a spacer. After forming the MOS transistor device, at least a first dummy contact is formed on a drain side of the gate and a gate contact is formed to be electrically connected to the gate. The first dummy contact is spaced apart from a surface of the substrate and electrically connected to the gate contact.

Abstract: According to an exemplary embodiment, a semiconductor device is provided. The semiconductor device includes: a substrate; a first vertical structure protruding from the substrate; a second vertical structure protruding from the substrate; an STI between the first vertical structure and the second vertical structure; wherein a first horizontal width between the first vertical structure and the STI is substantially the same as a second horizontal width between the second vertical structure and the STI.

Abstract: A method of forming a semiconductor device is disclosed. The method includes exposing a dummy oxide layer of a gate structure to a vapor mixture comprising NH3 and a fluorine-containing compound at a first temperature, wherein the dummy oxide layer is formed over a substrate and surrounded by a gate spacer that includes a material different from that of the dummy oxide layer. The method further includes rinsing the substrate with a solution containing de-ionized water (DIW) at a second temperature. The method may further include baking the substrate in a chamber heated to a third temperature higher than the first and second temperatures. The exposing, rinsing, and baking steps remove the dummy oxide layer thereby forming an opening in the gate spacer. The method may further include forming a gate stack having a high-k gate dielectric layer and a metal gate electrode in the opening.

Abstract: Methods for laser irradiation aluminum doping for monocrystalline silicon substrates are provided. According to one aspect of the disclosed subject matter, aluminum metal contacts are formed directly on a surface of a monocrystalline silicon substrate. The aluminum metal contact is selectively heated via laser irradiation, thereby causing the aluminum and a portion of the monocrystalline silicon substrate in proximity to the aluminum to reach a temperature sufficient to allow at least a portion of the silicon to dissolve in the aluminum. The aluminum and the portion of the monocrystalline silicon substrate in proximity to the aluminum is allowed to cool, thereby forming an aluminum-rich doped silicon layer on the monocrystalline silicon substrate.

Abstract: A laser annealing apparatus includes: a laser beam generator for providing a stable single-pulse laser; a cyclic delay unit (300) for splitting the single-pulse laser into several pulsed lasers; an optical module for converging one or more of the pulsed lasers on a substrate (204); and a movable stage (500) for providing the substrate (204) with movement in at least one degree of freedom. A laser annealing method includes: providing a stable single-pulse laser; splitting the single-pulse laser into several pulsed lasers according to a delay requirement and an energy ratio; and irradiating a substrate (204) successively with one or more of the pulsed lasers to keep a surface temperature of the wafer around the melting point or around a needed annealing temperature for a sufficiently long time during the annealing process, thus resulting in an improvement in both the laser energy utilization efficiency and effect of the annealing process.

Abstract: The present disclosure relates to an integrated microsystem with a protection barrier structure, and an associated method. In some embodiments, the integrated microsystem comprises a first die having a plurality of CMOS devices disposed thereon, a second die having a plurality of MEMS devices disposed thereon and a vapor hydrofluoric acid (vHF) etch barrier structure disposed between the first die and the second die. The second die is bonded to the first die at a bond interface region. The vHF etch barrier structure comprises a vHF barrier layer over an upper surface of the first die, and a stress reduction layer arranged between the vHF etch barrier layer and the upper surface of the first die.

Abstract: A highly reliable light-emitting device and a manufacturing method thereof are provided. A light-emitting element and a terminal electrode are formed over an element formation substrate; a first substrate having an opening is formed over the light-emitting element and the terminal electrode with a bonding layer provided therebetween; an embedded layer is formed in the opening; a transfer substrate is formed over the first substrate and the embedded layer; the element formation substrate is separated; a second substrate is formed under the light-emitting element and the terminal electrode; and the transfer substrate and the embedded layer are removed. In addition, an anisotropic conductive connection layer is formed in the opening, and an electrode is formed over the anisotropic conductive connection layer. The terminal electrode and the electrode are electrically connected to each other through the anisotropic conductive connection layer.

Abstract: Method of making at least one transistor strained channel semiconducting structure, comprising steps to form a sacrificial gate block and insulating spacers arranged in contact with the lateral faces of the sacrificial gate block, form sacrificial regions in contact with the lateral faces of said semiconducting zone, said sacrificial regions being configured so as to apply a strain on said semiconducting zone, remove said sacrificial gate block between said insulating spacers, replace said sacrificial gate block by a replacement gate block between said insulating spacers, remove said sacrificial regions, and replace said sacrificial regions by replacement regions in contact with the lateral faces of said semiconducting zone, on a semiconducting zone that will form a transistor channel region.

Abstract: A method of fabricating a semiconductor integrated circuit that includes forming a lower electrode in a semiconductor substrate, forming an interlayer insulating layer including a phase-change region exposing the lower electrode on the semiconductor substrate, forming a first phase-change layer having a crystalline state along surfaces of the interlayer insulating layer and an exposed lower electrode, and growing a second phase-change layer on the first phase-change layer based on the crystallinity of the first phase-change layer to be filled in the phase-change region.

Abstract: A method for transferring light-emitting elements onto a package substrate includes: providing a light-emitting unit including a temporary substrate and light-emitting elements; disconnecting the light-emitting elements from the temporary substrate to allow the light-emitting elements to float on a fluid; adjusting spacings between the light-emitting elements to have a predetermined size by controlling flow of the fluid; placing a package substrate into the fluid, followed by aligning the light-emitting elements with connecting pads of the package substrate so as to correspondingly place the light-emitting elements on the connecting pads; and removing the package substrate with the light-emitting elements from the fluid.