Abstract: Disclosed is a stacked variable inductors manufactured by stacking M (M?2) metal layers on a semiconductor substrate, and provides stacked variable inductors comprising, 1 to N inductors continuously connected in serial, wherein each of said inductors is formed on N (N?M) metal layers that are different each other; first and second ports each connected to the highest positioned inductor and to the lowest positioned inductor among said 1 to N inductors; and at least one MOSFET, and wherein one terminal of at least one MOSFET is connected to one of the first and second ports, and the other one is connected to one of adjacent terminals connected in serial between 1 to N inductors.

Abstract: In using an epitaxial growth method to selectively grow on a silicon substrate an epitaxial layer on which an element is to be formed, the epitaxial layer is formed so as to extend upward above a thermal oxide film that is an element isolating insulating film, in order to prevent formation of facets. Subsequently, unwanted portions of the epitaxial layer are removed by means of CMP to complete an STI element isolating structure.

Abstract: A process for forming a pattern according to the invention comprises steps of disposing a mask on a surface of a substrate, and irradiating a resist film with a first energy beam through the mask, forming a first resist pattern by developing the resist film after applying the first energy beam, irradiating the first resist pattern with a second energy beam without through the mask, forming a second resist pattern smaller than the first resist pattern by subjecting the first resist pattern to heat treatment after applying the second energy beam, and patterning the workpiece film by use of the second resist pattern as a mask. As a result, it is possible to provide a process for forming the resist pattern formed on the substrate which can be miniaturized with highly accurate control of size with ease beyond a resolution limit imposed by photolithographic techniques.

Abstract: Methods and arrangements are provided for significantly reducing electron trapping in semiconductor devices having a polysilicon feature and an overlying dielectric layer. The methods and arrangements employ a nitrogen-rich region within the polysilicon feature near the interface to the overlying dielectric layer. The methods include selectively implanting nitrogen ions through at least a portion of the overlying dielectric layer and into the polysilicon feature to form an initial nitrogen concentration profile within the polysilicon feature. Next, the temperature within the polysilicon feature is raised to an adequately high temperature, for example using rapid thermal anneal (RTA) techniques, which cause the initial nitrogen concentration profile to change due to the migration of the majority of the nitrogen towards either the interface with the overlying dielectric layer or the interface with an underlying layer.

Abstract: A fabrication method of a semiconductor package with a photosensitive chip is provided. A substrate having a core is prepared. An interposer is mounted on the substrate, with a peripheral portion of the substrate exposed from the interposer. A molding process is performed and the substrate is clamped between an upper mold and a lower mold, with the interposer received in an upwardly-recessed cavity of the upper mold. A molding compound is injected into the upwardly-recessed cavity to form a dam on the peripheral portion of the substrate. Then the upper and lower molds and the interposer are removed from the substrate to expose area covered by the interposer on the substrate. At least one photosensitive chip is mounted on the exposed area of the substrate. A lid seals the dam such that the chip is received in a space defined by the substrate, the dam and the lid.

Abstract: An access transistor, provided between a storage node in a memory cell and a bit line is formed of a P channel MOS transistor including P type first and second impurity regions formed in an N type well and a gate electrode. Buried interconnection is formed of metal having high melting point such as tungsten and provided stacked on a driver transistor formed on a main surface of a P type well and the access transistor. A polysilicon film forming a P channel TFT as a load element is formed on the buried interconnection, which is planarized, with an interlayer insulating film interposed.

Abstract: Systems and methods of passivating planar index-guided oxide vertical cavity surface emitting lasers (VCSELs) are described. These systems and methods address the unique susceptibility of these devices to damage that otherwise might be caused by moisture intrusion into the etch holes that are used to form the index-guiding confinement regions. In one aspect, a VCSEL includes a vertical stack structure having a substantially planar top surface. The vertical stack structure includes a top mirror, a bottom mirror, and a cavity region disposed between the top mirror and the bottom mirror and including an active light generation region. At least one of the top mirror and the bottom mirror has a layer with a peripheral region that is oxidized into an electrical insulator as a result of exposure to an oxidizing agent. The vertical stack structure defines two or more etched holes each extending from the substantially planar top surface to the oxidized peripheral region.

Abstract: A front plane laminate useful in the manufacture of electro-optic displays comprises, in order, a light-transmissive electrically-conductive layer, a layer of an electro-optic medium in electrical contact with the electrically-conductive layer, an adhesive layer and a release sheet. This front plane laminate can be prepared as a continuous web, cut to size, the release sheet removed and the laminate laminated to a backplane to form a display. Methods for providing conductive vias through the electro-optic medium and for testing the front plane laminate are also described.

Abstract: According to one exemplary embodiment, a bipolar transistor comprises a base having a top surface. The bipolar transistor further comprises a base oxide layer situated on top surface of the base. The bipolar transistor further comprises a sacrificial post situated on the base oxide layer. The bipolar transistor further comprises a conformal layer situated over the sacrificial post and top surface of the base, where the conformal layer has a density greater than a density of the base oxide layer. The conformal layer may be, for example, HDPCVD oxide. According to this exemplary embodiment, the bipolar transistor further comprises a sacrificial planarizing layer situated over the conformal layer. The sacrificial planarizing layer has a first thickness in a first region between first and second link spacers and a second thickness in a second region outside of first and second link spacers, where the second thickness is generally greater than the first thickness.

Abstract: A memory cell having improved interconnect. Specifically, a dynamic random access memory (DRAM) based content addressable (CAM) memory cell is provided. The lower cell plate of the storage capacitor is implemented to provide an interconnect for the access transistor and the CAM portion of the memory cell. Conductive plugs are coupled to each of the transistors and coupled directly to the lower cell plate of the capacitor.

Abstract: A method for forming an isolation layer of a semiconductor device which is capable of improving isolation characteristics of a highly integrated semiconductor device. The method includes the steps of forming a first insulating layer on a substrate; forming both a first recess in the first isolation region and a plurality of second recesses in the second isolation region by only once applying a photolithography process to the first insulating layer; forming a third recess, which is deeper than the first recess, in the center area of the first recess in the first isolation region; and filling the first, second, third recesses with insulating materials or a thermal oxide layer. In addition, in the semiconductor device includes isolation regions have different widths, wherein the first isolation region, which is relatively narrower in width than the second isolation region, has a deeper recess than the second isolation region.

Abstract: The invention is directed to a thin-film capacitor device that is adapted to be mounted on a printed wiring board together with an LSI device. After forming a plurality of grooves in a core substrate, a first conductive film is formed, and a first conductor is filled into each groove. After forming a metal film on the first conductive film, a dielectric film is generated by selective anodic oxidation of the metal film. A second conductive film is formed on the dielectric film, and an electrode connected to the second conductive film is formed. After removing the back surface of the core substrate until the grooves are exposed therein, an electrode for connection to the first conductor in each groove is formed. A capacitor is formed by the first conductive film and second conductive film sandwiching the dielectric film therebetween.

Abstract: The method for manufacturing a CMOS image sensor is employed to prevent bridge phenomenon between adjacent microlenses by employing openings between the microlenses. The method includes the steps of: preparing a semiconductor substrate including isolation regions and photodiodes therein obtained by a predetermined process; forming an interlayer dielectric (ILD), metal interconnections and a passivation layer formed on the semiconductor substrate in sequence; forming a color filter array having a plurality of color filters on the passivation layer; forming an over-coating layer (OCL) on the color filter array by using a positive photoresist or a negative photoresist; forming openings in the OCL by patterning the OCL by using a predetermined mask; and forming dome-typed microlenses on a patterned OCL.

Abstract: An interconnect substrate including a first substrate on which a first interconnect pattern is formed, having a mounting region for an electronic chip; and a second substrate on which a second interconnect pattern electrically connected to the first interconnect pattern is formed. The second substrate includes a region to which at least a part of the first substrate is adhered, and a mounting region for an electronic chip.

Abstract: The invention saves resources and energy. A cleaning/fluid-feeding head integrates a cleaning head portion and a fluid-feeding head portion. The cleaning head portion includes an organic substance cleaning unit, an inorganic substance cleaning unit, a rinsing unit and a drying unit. The organic substance cleaning unit, inorganic substance cleaning unit and rinsing unit selectively clean pattern forming regions on a substrate by feeding thereto a first cleaning fluid, second cleaning fluid and pure water, respectively. The drying unit dries the rinsed pattern forming regions by blowing hot air thereonto. The fluid-feeding head portion selectively feeds a liquid pattern forming material to the cleaned pattern forming regions.

Abstract: An integrated circuit package with lead fingers with a footprint on the order of the integrated circuit footprint is provided. A lead frame may be made from a metal sheet, which may be stamped or etched. The lead frame provides a plurality of posts and a connecting sheet connecting the plurality of posts. Dice are adhesively mounted to the plurality of posts. The dice have a conductive side with a plurality of conducting pads where each conducting pad is electrically and mechanically connected to a post. An encapsulating material is placed over the dice and lead frame, with the connecting sheet keeping the encapsulating material on one side of the lead frame. Parts of the connecting sheet are then removed, electrically isolating the posts. The integrated circuit packages formed by the encapsulated dice and leads may be tested as a panel, before the integrated circuit packages are singulated.

Abstract: Complementary metal-oxide-semiconductor (CMOS) integrated circuits with bipolar transistors and methods for fabrication are provided. A bipolar transistor may have a lightly-doped base region. To reduce the resistance associated with making electrical contact to the lightly-doped base region, a low-resistance current path into the base region may be provided. The low-resistance current path may be provided by a base conductor formed from heavily-doped epitaxial crystalline semiconductor. Metal-oxide-semiconductor (MOS) transistors with narrow gates may be formed on the same substrate as bipolar transistors. The MOS gates may be formed using a self-aligned process in which a patterned gate conductor layer serves as both an implantation mask and as a gate conductor. A base masking layer that is separate from the patterned gate conductor layer may be used as an implantation mask for defining the lightly-doped base region.

Abstract: A semiconductor device including a drift layer of a first conductivity type formed on a surface of a semiconductor substrate. A surface of the drift layer has a second area positioned on an outer periphery of a first area. A cell portion formed in the first area includes a first base layer of a second conductivity type, a source layer and a control electrode formed in the first base layer and the source layer. The device also includes a terminating portion formed in the drift layer including a second base layer of a second conductivity type, an impurity diffused layer of a second conductivity type, and a metallic compound whose end surface on the terminating portion side is positioned on the cell portion side away from the end surface of the impurity diffused layer on the terminal portion side.

Abstract: A semiconductor device has: a wiring board that includes an insulating substrate and a wiring provided on the insulating substrate; a semiconductor chip that is mounted on the wiring board; an opening that is formed at a predetermined position in the insulating substrate, one end of the opening being shut by the wiring to form the bottom of the opening; a thin film conductor that is formed on the surface of the wiring and at the bottom of the opening; an embedded conductor layer that is provided in the opening while contacting the thin film conductor formed at the bottom of the opening; and an external connection terminal that is disposed at the other end of the opening to electrically connect with the wiring through the embedded conductor layer and the thin film conductor provided in the opening.

Abstract: A capacitive structure (10). The capacitive structure comprises a semiconductor base region (30) having an upper surface, a well (12) formed within the semiconductor base region and adjacent the upper surface, a first dielectric layer (38) adjacent at least a portion of the upper surface, and a polysilicon layer (16) adjacent the first dielectric layer. The well, the first dielectric layer, and the first polysilicon layer form a first capacitor and are aligned along a planar dimension. The capacitive structure further comprises a first conductive layer (201) positioned with at least a portion overlying at least a portion of the polysilicon layer, a second dielectric layer (202) adjacent the first conductive layer, and a second conductive layer (203) adjacent the second dielectric layer. The first conductive layer, the second dielectric layer, and the second conductive layer form a second capacitor and are aligned along the planar dimension.