Abstract: Methods are provided for processing a substrate for depositing an adhesion layer having a low dielectric constant between two low k dielectric layers. In one aspect, the invention provides a method for processing a substrate including depositing a barrier layer on the substrate, wherein the barrier layer comprises silicon and carbon and has a dielectric constant less than 4, depositing a dielectric initiation layer adjacent the barrier layer, and depositing a first dielectric layer adjacent the dielectric initiation layer, wherein the dielectric layer comprises silicon, oxygen, and carbon and has a dielectric constant of about 3 or less.

Abstract: In a fabrication method for forming an electrical interconnection of CVD tungsten film, a contact hole is formed in a dielectric layer. A lower conductive layer is formed in the contact hole and over the dielectric layer. A portion of the lower conductive layer is removed. As a result, the dielectric layer is exposed. An upper conductive layer is formed over the lower conductive layer and over the dielectric layer. The lower conductive layer has a rough surface and the upper conductive layer has a smooth surface. In this manner, following patterning of conductive stripes over the conductive layer, residue is mitigated, and thus, inadvertent interconnection of neighboring stripes is eliminated.

Abstract: A structure and method for protecting exposed copper lines with chemisorbed, sacrificial, organic monolayers from further processing steps are herein described.

Abstract: A bonding column fabrication process for forming boding columns over a wafer. First, a mask layer is formed over the active surface of a wafer. The mask has a plurality of openings that exposes chip pads (or electrode pads) on the active surface of the wafer. A high-velocity physical metal deposition process is conducted to form at least one metallic material layer over the die pads (or electrode pads) inside the interior sidewalls of the openings. The metallic material layer inside the openings constitutes the bonding columns. Finally, the mask layer is removed and a surface layer is optionally formed over the exposed surface of the bonding columns.

Abstract: An electroluminescent device comprising: a first charge carrier injecting layer for injecting positive charge carriers; a second charge carrier injecting layer for injecting negative charge carriers; and a light-emissive layer located between the charge carrier injecting layers and comprising a mixture of: a first component for accepting positive charge carriers from the first charge carrier injecting layer; a second component for accepting negative charge carriers from the second charge carrier injecting layer; and a third, organic light-emissive component for generating light as a result of combination of charge carriers from the first and second components; at least one of the first, second and third components forming a type II semiconductor interface with another of the first, second and third components.

Abstract: The present invention relates to a solid electrolytic capacitor having a masking structure in which the insulation between the anode part and the cathode part can be ensured without fail, to its production method, to a method for coating a masking agent on a solid electrolytic capacitor substrate, and to an apparatus therefor. According to the present invention, the masking material covers the dielectric film on the metal material having valve action and sufficiently infiltrates into the core metal made of a metal having valve action while the solid electrolyte is masked by the masking material without fail, so that a solid electrolytic capacitor can be produced that has a reduced leakage current and a reduced stress generated at the reflow treatment or the like.

Abstract: A system, method and apparatus for processing a semiconductor device including a processing chamber and a heating assembly positioned within the processing chamber. The heating assembly including at least a plate defining an internal cavity configured to receive gas. The gas enters the internal cavity through a first passage at a first temperature, and exits the internal cavity at a second temperature through a second passage.

Abstract: A method of manufacturing a liquid crystal display device is intended to decrease the number of manufacturing steps. The liquid crystal display device is arranged so that in each pixel area provided on a liquid-crystal-side surface of one of a pair of substrates disposed to oppose each other with a liquid crystal interposed therebetween, a signal from a drain line is applied to a pixel electrode via a drain electrode and a source electrode which are formed in a layer overlying a semiconductor layer of a thin film transistor, by the supply of a scanning signal from a gate electrode which is positioned as an underlying layer with respect to the semiconductor layer.

Abstract: In an inverted stagger type thin-film transistor, the preparing process thereof can be simplified, and the unevenness of the thin film transistor prepared thereby can be reduced. That is, disclosed is a preparing method which comprises selectively doping a semiconductor on a gate insulating film with an impurity to form source, drain, and channel forming regions, and conducting a laser annealing to them, or a preparing method which comprises selectively doping the semiconductor region with an impurity by a laser doping method.

Abstract: A semiconductor component configured for wafer-level testing includes a semiconductor die having at least one die contact electrically exposed for coupling with a redistribution circuit that electrically couples at least one die contact to an extended contact such as a bumped contact. The component further includes a bus conductor that traverses at least a portion of the die and electrically mates with corresponding bus conductors on other similarly prepared components on the wafer. Functional and nonfunctional dice are identified on the wafer and the nonfunctional dice are isolated from the wafer-level testing grid. Following test, dice may be subsequently tested or moved to singulation wherein the die-to-die interconnection is interrupted, allowing wafer-level tested components to be conventionally assembled.

Abstract: A multiple chip module (MCM) for use with baseband, RF, or IF applications includes a number of active circuit chips having a plurality of different functions. The active circuit chips are mounted on a substrate that is configured to provide an integrated subsystem in a single MCM package. The MCM includes a number of features that enable it to meet electrical performance, high-volume manufacturing, and low-cost requirements. The MCM may incorporate split ground planes to achieve electronic shielding and isolation, vias configured as both thermal sinks and grounding connections, and specifically configured die attach pads and exposed ground conductor pads.

Abstract: The invention includes methods of forming a substrate having a surface comprising at least one of Pt, Pd, Co and Au in at least one of elemental and alloy forms. In one implementation, a substrate is provided which has a first substrate surface comprising at least one of Pt, Pd, Co and Au in at least one of elemental and alloy forms. The first substrate surface has a first degree of roughness. Within a chamber, the first substrate surface is exposed to a PF3 comprising atmosphere under conditions effective to form a second substrate surface comprising at least one of Pt, Pd, Co and Au in at least one of elemental and alloy forms which has a second degree of roughness which is greater than the first degree of roughness. The substrate having the second substrate surface with the second degree of roughness is ultimately removed from the chamber.

Abstract: A method of fabricating a nano silicon on insulator (SOI) wafer having an excellent thickness evenness without performing a chemical mechanical polishing (CMP) and a wafer fabricated by the same are provided. The provided method includes preparing a bond wafer and a base wafer, and forming a dielectric on at least on surface of the bond wafer. Thereafter, an impurity ion implantation unit is formed by implanting impurity ions into the bond wafer to a predetermined depth from the surface of the bond wafer at a low voltage. The dielectric of the bond wafer and the base wafer contact each other in order to be bonded. Next, a thermal process of low temperature is performed to cleave the impurity ion implantation unit of the bond wafer. In addition, the cleaved surface of the bond wafer bonded to the base wafer is etched to form a nano scale device region. Here, the cleaved surface may be etched by performing a hydrogen surface process and a wet etching.

Abstract: There is provided a MISFET which suppresses a short-channel effect in a deep submicron region and has a low parasitic resistance, a low parasitic capacitance, and a small drain junction leakage current. A shallow concave is formed in a channel forming portion and an extension region forming portion of a MISFET, shallow ion implantation for forming an extension region is performed to a bottom surface of the shallow concave. Deep ion implantation for forming a source/drain region is performed to a silicon substrate adjacent to the concave, and the position of a peak concentration of the shallow ion implantation is caused to coincide with the position of a peak concentration of the deep ion implantation, so that a MISFET which suppresses a short-channel effect and has a low source/drain parasitic resistance, a low source/drain parasitic capacitance, and a small drain junction leakage current generated by SALICIDE steps can be provided.

Abstract: An electrically and mechanically enhanced die-down tape substrate ball grid array (BGA) package substrate is described. An IC package includes a substrate that has a first surface. The first surface has a central opening. A stiffener/heat spreader has a first surface. The first surface of the stiffener has a central ground ring. The first surface of the stiffener is coupled to a second surface of the substrate. The central opening has an edge. The edge includes at least one of the following: (a) a protruding edge portion that extends across at least a portion of the central ground ring, (b) a recessed edge portion that exposes a portion of the central ground ring, or (c) a hole proximate to the edge, wherein the hole exposes a portion of the central ground ring.

Abstract: A method of controlling the top width of a deep trench. A conductive layer is formed on the trench over a substrate of polysilicon with a recessed structure. An additional layer of amorphous silicon (?-Si) is deposited onto the polysilicon. After subsequent oxidation, the amorphous silicon is converted to SiO2. According to the invention, the top width of a deep trench is controlled, protecting bit lines from sub-threshold leakage.

Abstract: A method of forming a memory cell with a single sided buried strap. A collar oxide layer is formed on the sidewall of a trench. A conductive layer fills the trench. The conductive layer and the collar oxide layer are partially removed to form an opening having first and second sidewalls. The remaining collar oxide layer is lower than the remaining conductive layer. An angle implantation with F ions is performed on the first sidewall. A thermal oxidation process is performed to form a first oxide layer on the first sidewall and a second oxide layer on the second sidewall. The first oxide layer is thicker than the second oxide layer. The second oxide layer is removed to expose the second sidewall. A buried strap is formed at the bottom of the opening, insulated from the first sidewall by the first oxide layer.

Abstract: A phase-change memory cell may be formed with a carbon-containing interfacial layer that heats a phase-change material. By forming the phase-change material in contact, in one embodiment, with the carbon containing interfacial layer, the amount of heat that may be applied to the phase-change material, at a given current and temperature, may be increased. In some embodiments, the performance of the interfacial layer at high temperatures may be improved by using a wide band gap semiconductor material such as silicon carbide.

Abstract: A multi-bit memory unit and fabrication method thereof. A semiconductor substrate forming a protruding semiconductor substrate is provided, an ion implantation region is formed on the semiconductor substrate beside the protruding semiconductor substrate, a spacer is formed on a sidewall of the protruding semiconductor substrate, a doped region is formed on the semiconductor substrate, and an ONO layer is conformally formed on the surface of the protruding semiconductor substrate, the spacer, the doped region, and the semiconductor substrate.

Abstract: The invention relates to a new type of encapsulated surface acoustic wave component and to a method for the batch production of such components. The component comprises a surface acoustic wave device on the surface of a substrate. The encapsulation package furthermore comprises the substrate, a first layer located on the substrate and hollowed out locally at least at the level of the active surface of the surface acoustic wave device, a printed circuit covering entire first layer and conductive via holes going through the unit formed by the first layer and the printed circuit so as to provide for the electrical connection of the surface acoustic wave device from the exterior.