Abstract: The mobility enhancement of a strained silicon layer is augmented through incorporation of carbon into a strained silicon lattice to which strain is also imparted by an underlying silicon germanium layer. The presence of the relatively small carbon atoms effectively increases the spacing within the strained silicon lattice and thus imparts additional strain. This enhancement may be implemented for any MOSFET device including silicon on insulator MOSFETs, and is preferably selectively implemented for the PMOS components of CMOS devices to achieve approximately equal carrier mobility for the PMOS and NMOS devices.

Abstract: The present invention relates to a method of manufacturing a transistor in a semiconductor device. In order to increase an upper area of a gate electrode in which a silicide layer will be formed, an upper portion of the gate electrode consisting of the polysilicon layer is formed to be wider than a lower portion while maintaining the channel length. Therefore, a sheet resistance characteristic of the silicide layer and the uniformity of the sheet resistance can be improved to this improve an electrical characteristic of a device.

Abstract: A bonding column fabrication process for forming boding columns over a wafer. First, a mask layer is formed over the active surface of a wafer. The mask has a plurality of openings that exposes chip pads (or electrode pads) on the active surface of the wafer. A high-velocity physical metal deposition process is conducted to form at least one metallic material layer over the die pads (or electrode pads) inside the interior sidewalls of the openings. The metallic material layer inside the openings constitutes the bonding columns. Finally, the mask layer is removed and a surface layer is optionally formed over the exposed surface of the bonding columns.

Abstract: A method for fabricating MEMS structures includes etching a recess in either an upper surface of a substrate that is bonded to a wafer that ultimately forms the MEMS structure, or to the lower surface of the wafer that is bonded to the substrate. Accordingly, once the etching processes of the wafer are completed, the recess facilitates the release of an internal movable structure within the fabricated MEMS structure without the use of a separate sacrificial material. Furthermore, a bridge, which is preferably insulating, is pre-etched before the wafer is attached to the substrate.

Abstract: A structure having trench isolation which protects a nitride liner in the trench during subsequent plasma processing. The structure includes a trench formed in a semiconductor substrate, the trench having sidewalls and a bottom. A thermal oxide layer is formed on the bottom and sidewalls of the trench so as to remove substrate damage caused during etching of the semiconductor substrate to form the trench. A material layer is formed on the thermal oxide layer so as to prevent the bottom and sidewalls of the trench from being oxidized. Then, a protection layer is formed on the oxidation barrier layer. The trench is filled with a trench fill material uniformly with respect to the bottom and sidewalls of the trench.

Abstract: This invention relates to a chemical vapor deposition process for forming Zr or Hf oxynitride films suitable for use in electronic applications such as gate dielectrics. The process comprises: a. delivering a Zr or Hf containing precursor in gaseous form to a chemical vapor deposition chamber, and, b. simultaneously delivering an oxygen source and a nitrogen source to the chamber separately, such that mixing of these sources with the precursor does not take place prior to delivery to the chamber, and, c. contacting the resultant reaction mixture with a substrate in said chamber, said substrate heated to an elevated temperature to effect deposition of the Zr or Hf oxynitride film, respectively. A silicon containing precursor may be added simultaneously to the chamber for forming Zr or Hf silicon oxynitride films.

Abstract: A semiconductor processing method of forming a conductive gate or gate line over a substrate includes, a) forming a conductive gate over a gate dielectric layer on a substrate, the gate having sidewalls and an interface with the gate dielectric layer; b) electrically insulating the gate sidewalls; and c) after electrically insulating the gate sidewalls, exposing the substrate to oxidizing conditions effective to oxidize at least a portion of the gate interface with the gate dielectric layer. According to one aspect of the invention, the step of exposing the substrate to oxidizing conditions is conducted after provision of a first insulating material and subsequent anisotropic etch thereof to insulate the gate sidewalls.

Abstract: Disclosed is a PIN photodiode used for a light-receiving element for optical communication. The PIN photodiode comprises a gate electrode structure consisting of a gate insulation layer and a gate electrode pad which prevent a bonding layer from being excessively depleted in the lateral direction at the time of applying a negative electric voltage to an electrode that is in contact with the bonding layer. The PIN photodiode allows the control of the electrostatic capacitance of the element by controlling the depletion level of the bonding layer in the lateral direction using the gate electrode pad. Therefore, it is possible to suppress the increase of the electrostatic capacitance and to achieve a high-speed operating property.

Abstract: In a method of fabricating a SiC semiconductor device, a surface of a SiC layer (5, 48, 102) is processed into a cleaned surface terminated at Si. An oxide film (7, 49, 105) is formed on the cleaned surface of the SiC layer. The SiC layer with the oxide film is subjected to thermal oxidation at a temperature in a range of 700° C. to 900° C. so that only terminal Si at the cleaned surface of the SiC layer is oxidated and an interface between the oxide film and the SiC layer becomes an SiO2/SiC cleaned interface.

Abstract: In a semiconductor integrated circuit device having a system-on-chip structure in which a DRAM and a logic integrated circuit are mixedly mounted on a chip, a silicide layer is formed on the surfaces of the source and the drain of a MISFET of a direct peripheral circuit of the DRAM, the surfaces of the source and the drain of a MISFET of an indirect peripheral circuit of the DRAM, and the surfaces of the source and the drain of a MISFET of the logic integrated circuit, and the silicide layer is not formed on the surfaces of the source and the drain of a memory cell selective MISFET of the memory cell of the DRAM.

Abstract: A method capable of removing dangling bonds generated on a surface of a photodiode is disclosed herein. The method includes steps of providing a semiconductor substrate having a light sensing area and removing dangling bonds at a surface of the light sensing area by diffusing hydrogen ions to the surface of the light sensing area.

Abstract: A plurality of p-wells and n-wells are formed in a front side of a bulk material, and a plurality of n layers and p layers are alternately formed within the bulk material between a back side of the bulk material and the plurality of n-wells and p-wells. The plurality of n layers are electrically isolated from one another and respectively route different potentials to selected ones of the plurality of n-wells, and likewise, the plurality of p layers are electrically isolated from one another and respectively route different potentials to selected ones of the plurality of p-wells.

Abstract: The invention is an apparatus and a method of manufacturing a structure. The method includes the step of patterning a layer to include a line and space pattern. A space of the line and space pattern in a first region includes a first critical dimension less than achievable at a resolution limit of lithography. A line of the line and space pattern in a second region includes a second critical dimension achievable at a resolution limit of lithography. A sidewall spacer is formed on a line from a masking layer used in the formation of the structure. The method uses one critical masking step and two non-critical masking steps.

Abstract: Gate dielectric degradation due to plasma damage during replacement metal gate processing is cured and prevented from further plasma degradation by treatment of the gate dielectric after removing the polysilicon gate. Embodiments include low temperature vacuum annealing after metal deposition and CMP, annealing in oxygen and argon, ozone or a forming gas before metal deposition, or heat soaking in silane or disilane, before metal deposition.

Abstract: There is provided a MISFET which suppresses a short-channel effect in a deep submicron region and has a low parasitic resistance, a low parasitic capacitance, and a small drain junction leakage current. A shallow concave is formed in a channel forming portion and an extension region forming portion of a MISFET, shallow ion implantation for forming an extension region is performed to a bottom surface of the shallow concave. Deep ion implantation for forming a source/drain region is performed to a silicon substrate adjacent to the concave, and the position of a peak concentration of the shallow ion implantation is caused to coincide with the position of a peak concentration of the deep ion implantation, so that a MISFET which suppresses a short-channel effect and has a low source/drain parasitic resistance, a low source/drain parasitic capacitance, and a small drain junction leakage current generated by SALICIDE steps can be provided.

Abstract: The present invention relates to a manufacturing method of a semiconductor device having a lid implemented on a semiconductor chip. The semiconductor device and the semiconductor device unit are capable of maintaining high thermal dissipation efficiency as well as the semiconductor chip having improved reliability. Specifically, upon manufacturing the above semiconductor device having a semiconductor chip mounted on a substrate and a lid thermally connected to this semiconductor chip, a stiffener, which controls the deformation of the semiconductor chip, is implemented on the side of the semiconductor chip that accommodates the lid; after which heating is performed so as to bond the semiconductor chip accommodating the stiffener to the substrate; followed by the bonding of the lid to the stiffener.

Abstract: Embodiments include semiconductor devices and a methods for manufacturing the same that suppress deficiencies in the transistor characteristics. A method for manufacturing a semiconductor device includes the steps of (A) forming a polishing stopper layer 14 having a predetermined pattern over a substrate 10, (B) removing a part of the substrate using the polishing stopper layer 14 as a mask to form a trench 16, (C) forming a trench oxide film 18 over a surface of the substrate 10 that forms the trench 16, (D) forming an insulating layer 21 that fills the trench 16 over an entire surface of the substrate, (E) polishing the insulating layer 21 by a chemical-mechanical polishing, (F) removing the polishing stopper layer 14, and (G) etching a part of the insulating layer 21 to form a trench insulating layer 20.

Abstract: A method is provided to deposit niobium monoxide gates. An elemental metal target, or a composite niobium monoxide target is provided within a sputtering chamber. A substrate with gate dielectric, for example silicon dioxide or a high-k gate dielectric, is provided in the sputtering chamber. The sputtering power and oxygen partial pressure within the chamber is set to deposit a film comprising niobium monoxide, without excess amounts of elemental niobium, NbO2 insulator, or Nb2O5 insulator. The deposition method may be incorporated into a standard CMOS fabrication process, or a replacement gate CMOS process.

Abstract: An active matrix substrate for a liquid crystal display and method of forming the same. To form the active matrix substrate five masks are needed. The first mask forms gate lines on the transparent substrate. The second mask patterns a stacked layer of a metal layer/an n-doped layer/a semiconductor layer formed on a gate insulating layer to form data lines. After forming a low k dielectric layer, the third mask forms openings therein. The forth mask patterns pixel electrodes and conducting lines with source pattern on the low k dielectric layer and further patterns the metal layer and the n-doped layer. After depositing a passivating layer the fifth mask defines the passivating layer.

Abstract: For temperature cycling at a material of an IC (integrated circuit) package, a laser beam is directed to the material such that the material absorbs the laser beam to become heated. A laser controller adjusts at least one property of the laser beam until the temperature of the material reaches a predetermined high-end temperature. The present invention may be used for a flip-chip IC package with the laser beam being directed toward a back-side of an IC die that is exposed on the IC package. In that case, the laser beam is comprised of light having a wavelength that is within a transmission region of a semiconductor material of the IC die such that the laser beam reaches the material on the front side of the IC die.