Abstract: A method of making a circuitized substrate for use in an electronic package wherein the substrate, e.g., ceramic, includes more than one conductive layer, e.g., copper, thereon separated by a suitable dielectric material, e.g., polyimide. Each layer includes its own conductive location(s) which are designed for being directly electrically connected, e.g. using solder, to respective contact sites on a semiconductor chip to form part of the final package. Significantly, the resulting package does not include interconnections between the conductive layers at the desired contact locations; these locations, as mentioned, instead being directly connected to the chip.

Abstract: Submicron-dimensioned MOS and/or CMOS transistors are fabricated by a process employing removable sidewall spacers made of a material, such as UV-nitride, which has been treated subsequent to its deposition, e.g., by ion implantation, to augment its etch rate with a room temperature etchant, e.g., dilute aqueous HF. The treated spacers are removed with the dilute, aqueous HF after implantation of moderately or heavily-doped source/drain regions but prior to any post-implantation annealing processing, in order not to increase the etch resistance of the spacer material by thermally-induced densification.

Abstract: A circuit element comprising a semiconductor substrate. A well region of a first conductivity type is formed in a surface of the substrate. A dielectric film is formed on the substrate. A gate conductor of the first conductivity type is formed on the dielectric film over the well region of the substrate. The gate conductor is formed of a polycrystalline silicon film. The gate conductor has an impurity concentration substantially lower than a standard impurity concentration for the gate conductor of an MOS device. A polycrystalline silicon edge spacer is formed on each side of the gate conductor. A first pair of first conductivity type impurity diffusion regions are formed adjacent to the polycrystalline silicon edge spacers. The polycrystalline silicon film and edge spacers lie on a portion of the substrate between the first pair of first conductivity type impurity diffusion regions.

Abstract: The present invention is directed to a simplified, CVD-less method of forming a barrier layer for a metal layer which prevents metal contamination in an integrated circuit. The invention utilizes a sacrificial multilayer dielectric structure and selective etching to form the top barrier layer. An opening is etched in the structure and a plating layer is deposited in the opening. A first unneeded portion of the structure along with an unneeded portion of the plating layer is removed utilizing an etchant that is selective for the first unneeded structural portion. A Cu layer is deposited and implanted with barrier material to form the top barrier layer. A second unneeded portion of the structure along with an unneeded portion of the top barrier layer is removed utilizing an etchant that is selective for the second unneeded structural portion. The resulting structure is a metal interconnect structure having an overlying top barrier layer which is produced without using CVD techniques.

Abstract: A method of manufacturing a semiconductor integrated circuit device comprises forming a gate insulating film on a surface of a semiconductor substrate of a first conductivity type, forming a polycrystal silicon film on the gate insulating film, etching the polycrystal silicon film to form a gate electrode on a portion of the gate insulating film, etching the gate insulating film except at the portion thereof where the gate electrode has been formed, and forming a thermal oxide film on the semiconductor substrate at regions corresponding to the etched gate insulating film. Impurities of a second conductivity type are implanted into a source region in the semiconductor substrate through the thermal oxide film to form a body region of the second conductivity type. The semiconductor substrate is then heated at a temperature of 1000° C. or higher.

Abstract: An improved semiconductor device and method which includes a zener diode and RC network combination that share common semiconductor mask steps during the fabrication process. A common N+ layer serves to provide both the separate N+ cathode regions of the zener diode and the separate bottom electrode N+ region of the capacitor. A common metal layer serves to provide separate electrical contacts to the N+ cathode regions of the zener diode and also provides a separate top metal electrode for the capacitor. The capacitor dielectric is comprised of silicon nitride. A silicon dioxide/silicon nitride insulation layer is formed between the top metal electrode of the capacitor and a resistive layer typically made from tantalum nitride.

Abstract: In thin film transistors (TFTS) having an active layer of crystalline silicon adapted for mass production, a catalytic element is introduced into doped regions of an amorphous silicon film by ion implantation or other means. This film is crystallized at a temperature below the strain point of the glass substrate. Further, a gate insulating film and a gate electrode are formed. Impurities are introduced by a self-aligning process. Then, the laminate is annealed below the strain point of the substrate to activate the dopant impurities. On the other hand, Neckel or other element is also used as a catalytic element for promoting crystallization of an amorphous silicon film. First, this catalytic element is applied in contact with the surface of the amorphous silicon film. The film is heated at 450 to 650° C. to create crystal nuclei. The film is further heated at a higher temperature to grow the crystal grains. In this way, a crystalline silicon film having improved crystallinity is formed.

Abstract: A method of forming dual damascene structure is disclosed. A pad oxide layer, a barrier layer and an organic dielectric layer are formed in sequence on a substrate with the conducting line and the organic dielectric layer is etched with a patterned photoresist as a mask to form trenches therein. Next, an anisotropic thickness oxide layer is formed on the substrate by the plasma enhanced chemical vapor deposition (PECVD). Then, the anisotropic thickness oxide layer, the barrier layer and the pad oxide layer are etched with a patterned photoresist as a mask to form vias therein until the conducting line is exposed. Finally, a metal layer is deposited on the substrate and fills the vias and the trenches to form the dual damascene structure.

Abstract: An improved structure and method are provided for signal processing. The structure includes dual-gated metal-oxide semiconducting field effect transistor (MOSFET). The dual-gated MOSFET can be fabricated according to current CMOS processing techniques. The body region of the dual-gated MOSFET is a fully depleted structure. The structure includes two gates which are positioned on opposite sides of the opposing sides of the body region. Further, the structure operates as one device where the threshold voltage of one gate depends on the bias of the other gate. Thus, the structure yields a small signal component in analog circuit applications which depends on the product of the signals applied to the gates, and not simply one which depends on the sum of the two signals.

Abstract: A method for forming a structure. A first dielectric material is deposited on a substrate. The first dielectric material is patterned. At least one metal is deposited in and on the first dielectric material. Portions of the at least one metal are removed at least in a region above an upper surface of the first dielectric material. The first dielectric material is removed. A second dielectric material is provided in place of first dielectric material.

Abstract: Silicon oxynitride layers are deposited by plasma enhanced chemical vapor deposition with significantly reduced defects, such as nodules, employing a ramp down step at the end of the deposition cycle. Embodiments include depositing a SION ARC at a first power, discontinuing the flow of SiH4 and ramping down to a second power while continuing the flow of N2O and N2, and ramping down to a third power while continuing the flow of N20 and N2 before pumping down. The resulting relatively defect free silicon oxynitride layers can be advantageously employed as an ARC, particularly when patterning contact holes in manufacturing flash memory devices.

Abstract: A semiconductor device manufacturing method for silicidizing silicon-containing areas in array regions of dynamic random access memory (DRAMS)and embedded DRAM (eDRAM) devices to lower electrical resistance, and improve device reliability at low temperatures.

Abstract: The present invention relates to a semiconductor device and a method of fabricating the same. A semiconductor device having first and second transistor regions and a field region includes a semiconductor substrate having a first type conductivity, a first trench in the substrate at the field region separating the first and second transistor regions from each other, a second trench in the substrate over the first trench, a first field oxide layer in the first trench, a second field oxide layer in the second trench over the first field oxide layer, first and second gate oxide layers on sides of the second trench, first and second gates in the second field oxide layer, and second and third impurity regions at the bottom surface of the second trench and first and fourth impurity regions outside the second trench on the substrate.

Abstract: In one aspect, the invention provides a method of forming a contact opening to a conductive line. In one preferred implementation, a contact opening is formed to a conductive line which overlies a substrate isolation area with an etch which also outwardly exposes substrate active area to accommodate source/drain doping. In another preferred implementation, desired PMOS regions over a substrate into which p-type impurity is to be provided are exposed while a contact opening is contemporaneously formed to at least one conductive line extending over substrate isolation oxide. In another preferred implementation, a contact opening to a conductive line over a substrate and an opening to a laterally spaced substrate active area are formed in a common masking step. In another preferred implementation, desired PMOS active areas over a substrate are exposed and p-type impurity to a first concentration is provided into desired exposed areas.

Abstract: The present invention provides a process for fabricating semiconductor device comprising the steps of: forming an etching-stop layer on a semiconductor substrate; patterning the etching-stop layer so that the etching-stop layer remains in a region to be an active region and is removed from a region to be a device isolation region, followed by forming a trench in the region to be the device isolation region; depositing on the semiconductor substrate an insulating film having a thickness greater than or equal to the depth of the trench; forming a resist pattern having an opening above the etching-stop layer above the active region adjacent to a device isolation region whose width is greater than or equal to a predetermined value, followed by etching the insulating film using the resist pattern as a mask; and polishing the insulating film existing on the resulting semiconductor substrate for flattening after removing the resist pattern.

Abstract: A complementary heterojunction field effect transistor (CHFET) in which the channels for the p-FET device and the n-FET device forming the complementary FET are formed from gallium antimonide (GaSb) or indium antimonide (InSb). An n-type HFET structure is grown, for example, by molecular beam epitaxy (MBE) in order to obtain the highest electron or hole mobility. The complementary p-type HFET is formed by p-type doping of a cap layer thereby eliminating the need for two implants for channel doping. In order to reduce the complexity of the process for making the CHFET, a common gold germanium alloy contact is used for both the p and n-type channel devices, thereby eliminating the need for separate ohmic contacts, resulting in a substantial reduction in the number of mask levels and, thus, complexity in fabricating the device.

Abstract: For fabricating a field effect transistor, a gate structure is formed on a gate dielectric on an active device area of a semiconductor substrate. An amorphization dopant and an extension dopant are implanted into exposed regions of the active device area to form drain and source extension junctions extending down to an extension depth within the semiconductor substrate. First and second spacers are formed at sidewalls of the gate structure. Any exposed regions of the active device area of the semiconductor substrate are etched down beyond the extension depth. The drain and source extension junctions remain disposed under the first and second spacers. A layer of doped amorphous semiconductor material is deposited to cover the structures on the semiconductor substrate and is doped with a contact dopant in an in-situ deposition process using a temperature of less than about 500° Celsius.

Abstract: Disclosed is a method for manufacturing a photovoltaic element wherein a pin-structure formed by laminating n-, i- and p-type semiconductor layers, each of which contains silicon atoms and has a non-monocrystalline crystal structure is formed at least one or more times on a substrate, the method comprising steps of forming each of the semiconductor layers and annealing the surface of at least one of the semiconductor layers or the substrate in an atmosphere of hydrogen gas, helium gas or argon gas that contains 1 to 1000 ppm of oxygen atom containing gas.

Abstract: An electrostatic discharge protection apparatus with silicon control rectifier and the method of fabricating the apparatus. Using silicon on insulator technique, a bottom layer, a P-well, a first source/drain region, a second source/drain region and a gate are formed. A selective epitaxial growth region is selectively formed on the first source/drain region, and an N+ region is formed on the bottom layer. The lower portion of the N+ region is then adjacent to the P-well, and the upper portion of the N+ region is adjacent to the gate. Thus, a PNPN silicon control rectifier is formed, and the silicon on insulation CMOS technique is effectively transplanted into the electrostatic discharge apparatus.

Abstract: A liquid crystal display having an increased pixel aperture ratio is disclosed along with a method of making same. An array of a-Si TFTs is deposited on a transparent substrate. Subsequently, an organic insulating layer (e.g. Benzocyclobutene) and a corresponding array of pixel electrodes are deposited over the TFT array so that the pixel electrodes overlap the display address lines thereby increasing the display's pixel aperture ratio. The low dielectric constant ∈ (e.g. about 2.7) and relatively high thickness (e.g. greater than about 1.5 &mgr;m) of the insulating layer reduce the pixel electrode-address line parasitic capacitance CPL in the overlap areas thereby reducing cross-talk (or capacitive coupling) in the display. In sum, an increased pixel aperture ratio is achieved without sacrificing display performance.