Abstract: An SRAM memory cell is provided having a pair of cross-coupled CMOS inverters. The sources of the pull-up transistors forming each of the CMOS inverters are coupled to VCC through parasitic resistance of the substrate in which each is formed. The source of the p-type pull-up transistor is therefore always at a potential less than or equal to the potential of the N-well such that the emitter-base junction of the parasitic PNP transistor cannot become forward biased and latch-up cannot occur.

Abstract: This invention is related to a thin film transistor (TFT) array and method of making same, for use in an active matrix liquid crystal display (AMLCD) having a high pixel aperture ratio. The TFT array and corresponding display are made by forming the TFTs and corresponding address lines on a substrate, coating the address lines and TFTs with a photo-imageable insulating layer which acts as a negative resist, exposing portions of the insulating layer with UV light which are to remain on the substrate, removing non-exposed areas of the insulating layer so as to form contact vias, and depositing pixel electrodes on the substrate over the insulating layer so that the pixel electrodes contact respective TFT source electrodes through the contact vias. The resulting display has an increased pixel aperture ratio because the pixel electrodes are formed over the insulating layer so as to overlap portions of the array address lines.

Abstract: A method for forming a laterally diffused metal-oxide semiconductor is disclosed. The invention normally is for forming a transistor device, which includes the following steps. Firstly a semiconductor layer is provided. Then a field insulating region is formed into the semiconductor layer. Sequentially forming a gate dielectric layer over a portion of the field insulating region is carried out. Then forming a deep portion of a first drain/source region within the semiconductor layer and spaced from the field insulating region/the top surface. Here, the deep portion is doped with dopants of a conductivity type, with the deep portion having a first doping concentration. The next step is forming a lightly doped portion of the first drain/source region within the semiconductor layer and a neighbouring portion of the field insulating region/the oxide top surface and adjacent the channel region. Generally the lightly doped portion is doped with dopants of the conductivity type.

Abstract: A vertically diffused FET (10) is fabricated on a semiconductor die (11) that includes an N+ substrate (12) and an N− epitaxial layer (14). The FET (10) has a source region (36) and a channel region (38) near a front surface (15) of the epitaxial layer (14), and a drain region in the substrate (12). A trench (22) extends through the epitaxial layer (14) to the substrate (12). A conductive layer (24) fills the trench (22), thereby forming a conductive plug (25) electrically coupled to the substrate (12). The conductive plug (25) forms a top side drain electrode of the FET (10).

Abstract: The present invention provides a method for forming a shaped floating gate on an integrated circuit substrate. A trench is etched in a surface of the integrated circuit substrate such that a tip is formed. The tip may be defined by a first sidewall that is approximately perpendicular to the surface of the integrated circuit substrate and a second sidewall that is disposed at an angle to the surface of the integrated circuit substrate. A dielectric layer is then formed over the substrate surface and conforming to the trench. Next, a conductive layer is deposited above the dielectric layer such that it fills the trench. The conductive layer is then etched such that a floating gate is defined. A bottom portion of the floating gate is then contained by the trench. The resulting floating gate and semiconductor device includes a dielectric layer disposed above an integrated circuit substrate surface. The substrate surface defines a trench having a tip that may be defined by a first sidewall and a second sidewall.

Abstract: The present invention is directed to an improved trench MOS gate device that comprises a trench whose floor and sidewalls include layers of dielectric material, the layers each having a controlled thickness dimension. These thickness dimensions are related by a controlled floor:sidewall layer thickness ratio, which is established by individually controlling the thickness of each of the floor and sidewall dielectric layers. This floor to sidewall layer thickness ratio is preferably at least 1 to 1, more preferably at least 1.2 to 1. Further in accordance with the present invention, a process for forming an improved trench MOS gate device comprises etching a trench in a silicon device wafer and forming layers of dielectric material on the trench floor and on the sidewalls, each layer having a controlled thickness dimension. The thickness dimensions are related by a controlled floor to sidewall layer thickness ratio that is preferably at least 1 to 1.

Abstract: A transistor (12) and method of making an integrated circuit (10) uses a chromium based sacrificial gate (22A) to align, dope and activate source and drain portions (36, 38, 52, 53,) of the transistor. The transistor is subjected to a high temperature to activate the source and drain, which would damage a high permittivity gate dielectric. The sacrificial gate is removed by etching with ceric ammonia nitrate. A high permittivity gate dielectric (72) and a final gate electrode (74) are formed over a channel (30) of the transistor. Electrodes (76, 78) are formed for coupling to the source and drain.

Abstract: According to an example embodiment, a semiconductor device having a back side and a circuit side opposite the back side is analyzed. The semiconductor device includes bulk silicon in the back side and also includes epitaxial silicon. An ion gas comprising SF6 and N2 is directed at a target region in the back side. Using the ion gas, the target region in the back side is selectively etched using reactive ion etching (RIE) and an exposed region is formed. The etching is selective to the bulk silicon. When the etching process encounters the epitaxial silicon, the etch rate slows and is used as an endpoint indicator of the selective etching process. Once the etching process is stopped, the circuitry is accessed via the exposed region.

Abstract: A nanometer-size quantum thin line is formed on a semiconductor substrate of a Si substrate or the like by means of the general film forming technique, lithographic technique and etching technique. By opportunely using the conventional film forming technique, photolithographic technique and etching technique, a second oxide film that extends in the perpendicular direction is formed on an Si substrate. Then, by removing the second oxide film that extends in the perpendicular direction, a second nitride film located below the film and a first oxide film located below the film by etching, a groove for exposing the Si substrate is formed. Then, a Si thin line is made to epitaxially grow on the exposed portion of the Si substrate. The quantum thin line is thus formed without using any special fine processing technique. The width of the groove can be accurately controlled in nanometers by controlling the film thickness of the second oxide film that is formed by oxidizing the surface of the second nitride film.

Abstract: A wafer boat that supports a plurality of semiconductor wafers at a predetermined pitch, which are to be processed by a vertical thermal processing furnace, comprises a plurality of support columns; wafer support grooves formed in the support columns for supporting the peripheral edges of the wafers; and a film thickness equalization plate that is substantially the same size as the wafers, or is larger than the wafers, and is provided in wafer support grooves that are adjacent to one another in the vertical direction. This configuration ensures the same type of film is formed on the surface facing the surface of the wafer, achieving uniformity of the thus-formed film thickness.

Abstract: There is disclosed a method of forming a buried strap (BS) and its quantum conducting barrier (QCB) in a structure wherein a doped polycrystalline silicon region is exposed at the bottom of a recess and separated from a monocrystalline region of a silicon substrate by a region of an insulating material. First, a thin continuous layer of undoped amorphous silicon is deposited by LPCVD to coat said regions. The surface of this layer is nitridized to produce a Si3N4 QCB film. Now, at least one dual layer comprised of an undoped amorphous silicon layer and a dopant monolayer is deposited onto the structure by LPCVD. The recess is filled with undoped amorphous silicon to terminate the buried strap and its QCB. Finally, the structure is heated to activate the dopants in the buried strap to allow an electrical continuity between said polycrystalline and monocrystalline regions through the QCB by a quantum mechanical effect. All these steps are performed in situ in the same LPCVD tool.

Abstract: To form a contact layer on source and drain electrodes of a stagger-type TFT, a conductive material is selectively sticked to the surface of the source and drain electrodes and a contact layer is selectively deposited by using the conductive material as growth species to form an active semiconductor layer on the contact layer. For an inverted-stagger-type TFT, a conductive material is selectively deposited on the surface of a contact layer to use the selectively deposited conductive material as source and drain electrodes so that patterning is unnecessary. To selectively deposit a contact layer of a TFT by alternately repeating etching and deposition, the temperature for the etching is set to 200° C. or lower. A contaminated layer on the surface of a semiconductor film serving as an active semiconductor layer and contact layer of a TFT is removed by plasma at the temperature of 200° C. or lower.

Abstract: A method and structure for forming an integrated circuit chip having multiple-thickness gate dielectrics includes forming a gate dielectric layer over a substrate, forming a sacrificial layer over the gate dielectric layer, forming first openings through the sacrificial layer to expose the gate dielectric layer in the first openings, growing a first gate dielectric having a thickness greater than that of the gate dielectric layer in the first openings, depositing a first gate conductor above the first gate dielectric in the first openings, forming a second opening through the sacrificial layer to expose the gate dielectric layer in the second opening, and depositing a second gate conductor in the second opening.

Abstract: An improvement to a process for manufacturing complementary metal oxide semiconductor devices on a monolithic substrate, where the improved process forms nonvolatile memory devices and programmable logic devices. The improvement includes exposing gate electrodes of a selected portion of the complementary metal oxide semiconductor devices at a point in the process where the gate electrodes have been previously covered by a protective material layer. A capacitive material layer is deposited on the monolithic substrate, such that it contacts the exposed gate electrodes of the selected portion of the complementary metal oxide semiconductor devices. A top electrode material layer is deposited on the monolithic substrate, such that the top electrode material layer contacts the capacitive material layer in a region overlying the exposed gate electrodes of the selected portion of the complementary metal oxide semiconductor devices.

Abstract: A method of fabricating a semiconductor device including MOS elements comprising the steps of forming: a gate insulation layer on a semiconductor substrate; forming a gate electrode on the gate insulation layer; and implanting impurity ions into source and drain forming regions, wherein the ion implantation into said source and drain forming regions is performed in separate ion implantation steps. In at least either one of the ion implantation steps for the source forming region or for the drain forming region, a resist layer used for blocking impurities is provided with a wall extending to said gate insulation layer at a location distant from said gate electrode, said wall allowing charges to flow to the substrate.

Abstract: Manufactured is a semiconductor device that has a substrate and a surface channel nMOS and a buried channel nMOS as well as a surface channel pMOS and a buried channel pMOS formed on the substrate. An n+ dopant is introduced prior to pattering a polycrystalline semiconductor layer that forms respective gate electrodes of the surface channel nMOS and the buried channel pMOS. A p+ dopant is also introduced prior to pattering a polycrystalline semiconductor layer that forms respective gate electrodes of the surface channel pMOS and the buried channel nMOS.

Abstract: A method for fabricating a mixed signal semiconductor device is disclosed.

Abstract: A new method of forming MOS transistors with shallow source and drain extensions and self-aligned silicide in the has been achieved. Gates are provided overlying a semiconductor substrate. Temporary sidewall spacers are formed on the gates. Ions are implanted into the semiconductor substrate and the polysilicon layer to form deep amorphous layers beside the spacers and shallow amorphous layers under the spacers. The spacers are removed. Ions are implanted to form lightly doped junctions in the shallower amorphous layer. Permanent sidewall spacers are formed on the gates. Ions are implanted to form heavily doped junctions in the deeper amorphous layer. A metal layer is deposited. A capping layer is deposited to protect the metal layer during irradiation. The integrated circuit device is irradiated with laser light to melt the amorphous layer while the crystalline polysilicon and semiconductor substrate remain in solid state.

Abstract: There is provided a MISFET which suppresses a short-channel effect in a deep submicron region and has a low parasitic resistance, a low parasitic capacitance, and a small drain junction leakage current. A shallow concave is formed in a channel forming portion and an extension region forming portion of a MISFET, shallow ion implantation for forming an extension region is performed to a bottom surface of the shallow concave. Deep ion implantation for forming a source/drain region is performed to a silicon substrate adjacent to the concave, and the position of a peak concentration of the shallow ion implantation is caused to coincide with the position of a peak concentration of the deep ion implantation, so that a MISFET which suppresses a short-channel effect and has a low source/drain parasitic resistance, a low source/drain parasitic capacitance, and a small drain junction leakage current generated by SALICIDE steps can be provided.

Abstract: Wells of n- and p-type are formed in a p-type substrate. Wells of p-type are also formed in the n-type well. Both the p-type wells are formed by the same process at the same time to make MOS transistors have different threshold voltages. MOS transistors having a long gate length and a low threshold voltage are formed in the p-well in the n-well, and MOS transistors having a short gate length and a high threshold voltage are formed in the p-well at the outside of the n-well. Fuses are formed over the p-type wells in the n-type well at a high density.