Abstract: A method for manufacturing a cell capacitor includes a step of forming an upper electrode and a trench for the lower electrode simultaneously in a single mask step. Further steps for manufacturing a cell capacitor includes forming a storage node contact by employing a predefined plate silicon layer and forming a capacitor dielectric using the storage contact node, as a result, it becomes possible to resolve “lift-off” problems, twin-bit failures, and misalignment.

Abstract: A method of fabricating a MOS capacitor in a complementary MOS fabrication process with dual-doped poly gates comprises providing a substrate of a first conductive type, the substrate having a first well of the first conductive type and a second well of a second conductive type. A dielectric layer is formed on the substrate. A first poly gate of the first conductive type is formed on the dielectric layer over the first well and a second poly gate of the second conductive type is formed on the dielectric layer over the second well. A first doped region of the first conductive type is formed in the substrate at each side of the first poly gate. A second doped region of the second conductive type is formed in the substrate at each side of the second poly gate layer. A spacer is formed on sidewalls of the first poly gate and the second poly gate, wherein a portion of the dielectric layer is also removed to expose a portion of the first doped region and a portion of the second doped region.

Abstract: A method for integrating the zero-etch and STI-etch processes into one process is described. An etch stop layer is deposited on a substrate. A mask is formed overlying the etch stop layer having a first opening for a planned alignment mark and having a second opening for a planned shallow trench isolation region. The etch stop layer is etched away within the first and second openings and the semiconductor substrate exposed within the first and second openings is etched into a first depth to form a first trench underlying the first opening and a second trench underlying the second opening. The first trench is covered and the second trench is etched into the semiconductor substrate to a second depth greater than the first depth. The second trench is filled to complete formation of a shallow trench isolation region wherein the first trench completes formation of an alignment mark in the fabrication of an integrated circuit device.

Abstract: A method of providing isolation between active areas of memory cells in a memory device having a plurality of isolation trenches (115) separating the active areas, comprising depositing a first insulating material (116) and forming a resist (120) over the first insulating material (116) over at least the trenches (115), leaving a first top portion of the first insulating material (116) exposed. At least a second top portion of the first insulating material (116) is removed, the resist (120) is removed, and a second insulating material (216) is deposited over the wafer (100) to completely fill the isolation trenches (115).

Abstract: A method of manufacturing a semiconductor device in which an increase in a parasitic resistance can be prevented, resulting in prevention of a deterioration in a current driving capability and a reduction in an operating speed of a semiconductor integrated circuit in consideration of an influence of etching of a semiconductor substrate on an NMOS transistor. By using a gate electrode as an implantation mask, an arsenic or phosphorus ion is implanted into a silicon substrate to form a pair of extension layers in a surface of the silicon substrate. Then, a protective insulating film having a thickness of 1 to 20 nm is formed with a silicon oxide film by a CVD method over the whole surface of the silicon substrate. Thereafter, a boron or BF2 ion is implanted into the silicon substrate from above the protective insulating film by using a gate electrode as an implantation mask. Thus, a pair of extension layers are formed in the surface of the silicon substrate.

Abstract: A power MOSFET is provided that includes a substrate of a first conductivity type. An epitaxial layer also of the first conductivity type is deposited on the substrate. First and second body regions are located in the epitaxial layer and define a drift region between them. The body regions have a second conductivity type. First and second source regions of the first conductivity type are respectively located in the first and second body regions. A plurality of trenches are located below the body regions in the drift region of the epitaxial layer. The trenches, which extend toward the substrate from the first and second body regions, are filled with a thin oxide layer and a polycrystalline semiconductor material (e.g., polysilicon) that includes a dopant of the second conductivity type.

Abstract: An active matrix circuit using top-gate type thin-film transistors is characterized in that an auxiliary capacitor is formed between a black matrix and an N-type or P-type active layer, and uses, as a dielectric, a silicon nitride layer used as a passivation film of an interlayer insulator. Also, an active matrix circuit using bottom-gate type thin-film transistors is characterized in that two auxiliary capacitors. One of the auxiliary capacitors is formed between a capacitor wiring line formed on a substrate and an N-type or P-type conductive region or a metal wiring line connected to the conductive region, and uses a gate insulating film as a dielectric. The other one of the auxiliary capacitors is formed between a black matrix and said N-type or P-type conductive region or said metal wiring line connected to the conductive region, and uses a silicon nitride layer used as a passivation film as a dielectric.

Abstract: A semiconductor device has, in one embodiment, two wells of different conductivity types formed in a semiconductor substrate. The two wells are arranged to be adjacent to each other to form a junction therebetween. A field oxide film is formed to cover the junction at a main surface of the semiconductor substrate. Other field oxide films or field-shield isolation structures may be formed to isolate circuit elements from one another in the wells.

Abstract: An integrated circuit device is fabricated by forming at least one isolation region in an area of a semiconductor substrate, such as a monolithic semiconductor substrate or a silicon on insulator (SOI) substrate. The at least one isolation region defines at least one active region. A plurality of dummy conductive regions is distributed in the area of the semiconductor substrate, with the dummy conductive regions being constrained to overlie the at least one isolation region. The dummy conductive regions may be formed from a conductive layer that is also used to form, for example, a gate electrode, a capacitor electrode or a wiring pattern. The dummy conductive regions may be formed on an insulation layer, e.g., a gate insulation layer or an interlayer dielectric layer. Preferably, the dummy conductive regions are noncontiguous. In one embodiment, a lattice-shaped isolation region is formed including an array of node regions linked by interconnecting regions and defining an array of dummy active regions.

Abstract: A method for the formation of rhodium films with good step coverage is disclosed. Rhodium films are formed by a low temperature atomic layer deposition technique using a first gas of rhodium group metal precursor followed by an oxygen exposure. The invention provides, therefore, a method for forming smooth and continuous rhodium films which also have good step coverage and a reduced carbon content.

Abstract: To decrease the thickness of a silicon thin film to a desired value without deterioration of the quality thereof while avoiding the surface roughness due to speed increasing oxidation of crystal defect portions occurring when conducting the conventional sacrificial oxidation, effect of dust particles, etc. and also avoiding deterioration of high pressure resistance of the oxide film associated with the surface roughness. A silicon ultrathin film SOI layer is produced in the following two steps: preparing a SOI wafer having a silicon thin film, which exhibits less precipitation of oxygen, thereon by the SIMOX method or the semiconductor bonding method, and cleaning the SOI wafer with an alkali solution such as SC1 and TMAH, so as to utilize the etching action of the aqueous cleaner.

Abstract: Disclosed herein is a method for the fabrication of a capacitor of semiconductor device, which is capable of increasing a charge storage capacitance of the capacitor while generation of leakage current in the capacitor. The method comprises the steps of: forming a ruthenium film as a lower electrode on a semiconductor substrate; forming a TaON film having a high dielectric constant on the ruthenium film; and forming a upper electrode on the TaON film.

Abstract: A method of etch polysilicon adjacent to a recessed STI structure feature is described. A substrate is provided with a dielectric layer thereon and a polysilicon layer on the dielectric layer. A shallow trench is formed that extends through the polysilicon and dielectric layers into the substrate. An insulating material is used to fill the trench and is then recessed in the trench below the surface of the substrate by polishing and etching steps. A conformal buffer layer is deposited which covers the polysilicon and sidewalls of the trench above the recessed insulating layer. The buffer layer is etched back to expose the insulating layer and the polysilicon is removed by a plasma etch. A spacer comprised of a portion of the buffer layer protects the substrate during the polysilicon etch to prevent unwanted trenches from being formed adjacent to the STI structure, thereby increasing the etch process window.

Abstract: Methods and apparatuses for efficiently forming a homogeneous glass layer having uniform thickness and a homogeneous metal layer having uniform thickness are provided. A workpiece is accommodated in a screened container which is rotatable in a predetermined direction. The workpiece in the container is sprayed with an atomized glass slurry or an atomized metal slurry while the container is rotated in order to form a green glass layer or a green metal layer on the workpiece. Simultaneously, hot air is supplied to the workpiece so as to dry the green glass layer or the green metal layer. Thus, the workpiece, typically a ferrite core, can be provided with a homogeneous layer having a uniform thickness. A method for manufacturing an electronic component using the above-described methods and apparatuses is also provided.

Abstract: A method and semiconductor structure including silicon-on-insulator (SOI) devices are provided for implementing reach through buried interconnect. A semiconductor stack includes a predefined buried conductor to be connected through multiple insulator layers and at least one intermediate conductor above the predefined buried conductor. A hole is anisotropically etched through the semiconductor stack to the predefined buried conductor. The etched hole extends through the at least one intermediate conductor and the insulators to the predefined buried conductor in the semiconductor stack. A thin layer of insulator is deposited over an interior of the etched hole. The deposited thin insulator layer is anisotropically etched to remove the deposited thin insulator layer from a bottom of the hole exposing the predefined buried conductor in the semiconductor stack with the thin insulator layer covering sidewalls of the hole to define an insulated opening.

Abstract: Steep concentration gradients are achieved in semiconductor device of small sizes formed on SOI or double SOI wafers by using implanted polycrystalline material such as polysilicon as a solid diffusion source. Rapid diffusion of impurities along grain boundaries relative to diffusion rates in monocrystalline materials provides a substantially constant impurity concentration at the interface between polycrystalline material and monocrystalline material. Steepness of the impurity concentration gradient is thus effectively scaled as transistor size is decreased to counter increased short channel and other deleterious effects. In the case of SOI wafers greater uniformity of electrical characteristics are achieved using the high quality of semiconductor material made available therein consistent with the relatively thin active layer.

Abstract: A pixel device comprising an electrochemical transistor device with a source and a drain contact; a gate electrode; an electrochemically active element in direct electrical contact with source and drain contacts, and comprising a transistor channel comprising an organic material; and a solidified electrolyte in direct electrical contact with the active element, and an electrochromic device comprising an electrochromic element comprising a material conducting in at least one oxidation state and an electrochromic material; a solidified electrolyte layer in direct electrical contact with the electrochromic element; and two electrodes for application of a voltage and in direct electrical contact with a component selected from the electrolyte layer(s); in which one of the source and drain contacts of the electrochemical transistor device is in electrical contact with one of the electrodes of the electrochromic device.

Abstract: A novel method and structure are described for making capacitor-under-bit line (CUB) DRAM cells with improved overlay margins between bit lines and capacitor top electrodes. After insulating the FETs with a first insulating layer, a second insulating layer is deposited and first openings are etched for capacitor bottom electrodes. A first conducting layer is deposited. The second openings are recessed to the first conducting layer. The first conducting layer is removed and the underlying second insulating layer is recessed. A thin interelectrode layer is deposited. A second conducting layer is deposited to fill the first and second openings, and is polished back to form a novel structure having capacitor top plates that are auto-self-aligned to the second insulating layer over the bit-line contacts. This allows for increased overlay margins and increases cell density.

Abstract: A method for forming a dielectric layer provides that a oxidizable substrate has formed thereupon a thermal oxide layer in turn having formed thereupon a deposited nitride layer. The deposited nitride/thermal oxide stack layer is then sequentially: (1) annealed within a nitriding atmosphere; (2) annealed within an oxidizing atmosphere; and (3) treated with a vaporous hydrofluoric acid atmosphere. The annealed and treated stack layer provides, for example, a gate dielectric layer with diminished thickness and enhanced performance.

Abstract: The method of forming a capacitor of a semiconductor device comprises the steps of forming a semiconductor film connected to a semiconductor substrate, forming a capacitor lower electrode made of a tungsten film selectively on a surface of the semiconductor film by causing a tungsten compound gas to react with the semiconductor film, forming a tungsten nitride film by nitriding a surface of the tungsten film by using a nitrogen gas or a nitrogen containing gas, forming a capacitor dielectric film made of oxygen compound on the tungsten nitride film, annealing the capacitor dielectric film in an oxygen containing gas, and forming a capacitor upper electrode made of a conductive film on the capacitor dielectric film.