Abstract: A semiconductor device has, in one embodiment, two wells of different conductivity types formed in a semiconductor substrate. The two wells are arranged to be adjacent to each other to form a junction therebetween. A field oxide film is formed to cover the junction at a main surface of the semiconductor substrate. Other field oxide films or field-shield isolation structures may be formed to isolate circuit elements from one another in the wells.

Abstract: Test structures for a high voltage MOSFET are provided that includes a substrate of a first conductivity type. An epitaxial layer also of the first conductivity type is deposited on the substrate. A plurality of trenches are located in the drift region of the epitaxial layer. The trenches, which extend toward the substrate from the first and second body regions, are filled with a material that includes a dopant of the second conductivity type. The dopant is diffused from the trenches into portions of the epitaxial layer adjacent the trenches. The test structures allow the simultaneous optimization of the breakdown voltage and on-resistance of the device.

Abstract: There is suggested a method for forming a good-quality polysilicon layer having a large area through a low temperature process even if laser annealing is not conducted. An object of the present invention is therefore to provide a poly-Si TFT array substrate exhibiting little display unevenness and having a high exactitude even if it has a large screen. This object can be attained by a method for producing a TFT array substrate for a liquid crystal display device, comprising a process of forming, on a substrate, a poly-Si TFT in which a polysilicon semiconductor layer is used in a channel area, comprising a polysilicon layer forming step of depositing silicon particles excited by adding energy beforehand onto the substrate so that the polysilicon layer is formed at the stage when the silicon particles are deposited on the substrate.

Abstract: In a semiconductor device of this invention, a pillar projection serving as a very thin active region is formed on the surface of a p-type silicon semiconductor substrate. A gate electrode 21 is formed to cover a central portion of the pillar projection. A pair of impurity diffusion layers 22 are formed on the pillar projection on the two sides of the gate electrode. An element isolation insulating film 23 is formed to sandwich and bury the side surfaces of the pillar projection. This semiconductor device has high performance equivalent to that of an SOI structure. The semiconductor device of this invention has three channels corresponding to a pair of a source and a drain, is selectively formed on the same semiconductor substrate as a common bulk transistor, and has a very fine structure and high drivability.

Abstract: A method of manufacturing a LDHOS transistor having a dielectric block under the gate electrode. A high voltage well, low voltage well (LV PW), and field oxide regions having bird beaks are provided in a substrate and overlay the high voltage well and the low voltage well. In a key step, a dielectric block is formed over the bird beaks of the field oxide regions. A gate is formed over the dielectric block. After this the LDMOS device is completed. The invention's dielectric block covers the bird's beaks of the field oxide regions and enhances the e-field tolerance. The invention's e-field enhancement dielectric block relieves the e-field near the bird's beak, thus increasing the breakdown voltage of the transistor.

Abstract: A semiconductor device has a semiconductor substrate having a peripheral circuit area and a memory cell area. A border region having a well of a first conductivity is formed between the peripheral circuit area and the memory cell area. A well of a second conductivity is formed in the peripheral circuit area. The well in the peripheral circuit area is in contact with the border region but not in contact with the memory cell area. Dummy transistors are formed in the border region. The dummy transistors are arranged with substantially the same transistor forming density as that of the memory cell area.

Abstract: This invention relates to a method for forming the salicide, more particularly, to the method for forming the salicide in the partial region. The present invention uses a nitride layer to be the mask layer to form the salicide in the partial region of the logic circuit. The silicide is formed on the gate and is not formed in the diffusion region, which are in the cell array region. The silicide is formed on the gate and in the diffusion region, which are in the periphery region. The present invention method can make the semiconductor device obtain lower resistance and decrease the leakage defects.

Abstract: A sensor, such as a mass spectrometer, capable of detecting the presence of materials in a sampled gas is interconnected with a processing chamber of a vacuum manufacturing tool. The sensor includes a timing circuit which is activated only if certain levels of specific materials are detected. Furthermore, the timer is set to run a predetermined time interval after activation so as to discriminate between known transient processing conditions and the presence of impurities which can greatly influence the manufacturing process. When the timer exceeds the predetermined time duration, an output signal can alert the process operator or automatically shutdown the manufacturing tool.

Abstract: A semiconductor device fabrication method comprises the steps of forming a gate insulating film on a surface of a semiconductor substrate, forming a polysilicon film on the gate insulating film, and implanting B or BF2 impurity ions into the polysilicon film. The polysilicon film is then heat-treated at a temperature of 700-900° C. to activate and diffuse the implanted B or BF2 impurity ions. Thereafter, a silicide film is formed on the heat-treated polysilicon film. The silicide film and the heat-treated polysilicon film are then etched to form a gate electrode on the gate insulating film. A CVD-grown dielectric film having a thickness of 5 to 1000 Å is then formed over the whole surface of the semiconductor substrate and the gate electrode. B or BF2 impurity ions are then implanted into the surface of the semiconductor substrate, using the gate electrode as a mask, to form source/drain regions.

Abstract: Methods and structures for determining alignment during semiconductor wafer processing are described. In one implementation, two geometric shapes are formed at different elevations over a substrate and at least partially overlapping with one another. The two shapes are inspected for overlap to determine whether the two shapes are misaligned. If the shapes are misaligned, a magnitude of misalignment is determined from the degree of overlap of the two shapes. In another implementation, a pair of elevationally spaced-apart geometric shapes are used to translate shifts of the shapes in one direction into quantifiable shift magnitudes using another direction. In yet another implementation, shifts in both the X and Y direction are readily quantifiable through visual inspection.

Abstract: The present invention provides a method for fabricating improved integrated circuit devices. The method of the present invention enables selective hardening of gate oxide layers and includes providing a semiconductor substrate having a gate oxide layer formed there over. A resist is then formed over the gate oxide layer and patterned to expose one or more areas of the gate oxide layer which are to be hardened. The exposed portions of the gate oxide layer are then hardened using a true remote plasma nitridation (RPN) scheme or a high density plasma (HDP) RPN scheme. Because the RPN scheme used in the method of the present invention runs at low temperature, the patterned resist remains stable through the RPN process, and those areas of gate oxide layer which are exposed by the patterned resist are selectively hardened by the RPN treatment, while those areas covered by the patterned resist remain unaffected.

Abstract: The present invention provides a method for forming capacitor of a dynamic random access memory cell. The method comprises providing a substrate and the word line structures formed thereon. A first dielectric layer is deposited on the substrate and the word line structures. A first polysilicon layer is deposited to form bit line contacts and bit lines. A second dielectric layer is formed on the first dielectric layer and the bit lines. The partial second dielectric layer is removed to form at least a wall structure in the second dielectric layer. The partial second dielectric layer and partial first dielectric layer are removed to form a capacitor contact opening. A second polysilicon is deposited into the capacitor contact opening and on the wall structure and the second dielectric layer. The partial second polysilicon is removed to form a capacitor node whereby a side-wall of the capacitor node is adjacent to the wall structure.

Abstract: Methods of manufacturing integrated circuit capacitors include the steps of forming a first electrically insulating layer having an opening therein, on a semiconductor substrate and then forming an electrically conductive electrode layer on an upper surface of the first electrically insulating layer and on a sidewall of the opening within the first electrically insulating layer. The electrically conductive electrode layer is then covered with a second electrically insulating layer. The second electrically insulating layer and the electrically conductive electrode layer are then planarized to expose the upper surface of the first electrically insulating layer and define a capacitor electrode layer on the sidewall of the opening. The capacitor electrode layer is then selectively etched back to expose the sidewall of the opening and define a lower capacitor electrode that is recessed relative to the upper surface of the first electrically insulating layer.

Abstract: A trenched field effect transistor suitable especially for low voltage power applications provides low leakage blocking capability due to a gate controlled barrier region between the source region and drain region. Forward conduction occurs through an inversion region between the source region and drain region. Blocking is achieved by a gate controlled depletion barrier. Located between the source and drain regions is a fairly lightly doped body region. The gate electrode, located in a trench, extends through the source and body regions and in some cases into the upper portion of the drain region. The dopant type of the polysilicon gate electrode is the same type as that of the body region. The body region is a relatively thin and lightly doped epitaxial layer grown upon a highly doped low resistivity substrate of opposite conductivity type. In the blocking state the epitaxial body region is depleted due to applied drain-source voltage, hence a punch-through type condition occurs vertically.

Abstract: In a thin film transistor, a first insulating film on a silicon layer formed in an island on a substrate is smaller in thickness than the silicon layer so that the stepped island edges is gentle in slope to facilitate covering the island with a second insulating film. This reduces occurrence of gate leak considerably. Since the peripheral region of the stepped island is smaller in thickness than the central region above the channel, it is possible to minimize occurrence of gate electrode breakage. The silicon layer contains two or more inert gas atoms, and the atoms smaller in mass number (e.g., He) are contained in and near an interface with a silicon active layer while the atoms larger in mass number (e.g., Ar) than those smaller in mass number are contained in and near a second interface with a gate electrode.

Abstract: A method of forming an anti-reflective coating material layer in the fabrication of integrated circuits includes providing a substrate assembly having a surface and providing an inorganic anti-reflective coating material layer on the substrate assembly surface. The inorganic anti-reflective coating material layer has an associated first etch rate when exposed to an etchant. The method further includes thermally treating the inorganic anti-reflective coating material layer formed thereon such that the thermally treated anti-reflective coating material layer then has an associated second etch rate less than the first etch rate when exposed to the etchant, e.g., the second etch rate is less than 16 Å/minute, the second etch rate is less than 20% of the first etch rate, etc.

Abstract: The present invention is characterized by providing epitaxial growth of a semiconductor layer on the surface of a wafer not provided with mirror finishing and having irregularity, introducing impurities having different conductivity type in the epitaxially grown semiconductor layer to form at least a pn junction, and further providing rapid thermal anneal by rapid heating-up and rapid cooling-down in any step in the manufacturing process. By so processing, there can be obtained a semiconductor device having high speed switching characteristics in stable manner without causing problems in manufacturing process such as diffusion of heavy metal or irradiation of corpuscular ray.

Abstract: An improved method for reducing the cost of fabricating bottle-shaped deep trench capacitors.

Abstract: A combined preanneal/oxidation step using a rapid thermal process (RTP) for treatment of a silicon wafer to form a thermal oxide of a given thickness while simultaneously adjusting the denuded zone depth and bulk micro defect density (BMD) comprising: exposing the wafer to a controlled temperature and a controlled preannealing time in an oxidation ambient at ambient pressure to obtain a target thermal oxide thickness that is preselected to correspond to a preselected denuded zone depth.

Abstract: A split-gate p-channel memory cell of an EEPROM, and method of fabricating the cell, are provided. The memory cell includes a memory transistor and select transistor that share a common gate. It further includes two independent and distinct threshold voltage adjusts implanted in different portions of a channel region of a substrate of the memory cell. One of the threshold voltage adjusts is disposed in relation to the memory transistor so as to influence its threshold voltage. The other threshold voltage adjust is disposed in relation to the selected transistor so as to influence its threshold voltage. In the method of fabrication, an n-type of dopant is implanted into the substrate to form the threshold voltage adjust associated with the memory transistor and a p-type of dopant is implanted into the substrate to form the threshold voltage adjust associated with the select transistor.