Abstract: In one aspect of the invention, a semiconductor processing method includes: a) providing a semiconductor substrate; b) defining a first conductivity type region and a second conductivity type region of the semiconductor substrate; c) providing a first transistor gate over the first type region which defines a first source area and a first drain area operatively adjacent thereto; d) providing a second transistor gate over the second type region which defines a second source area and a second drain area operatively adjacent thereto; and e) blanket implanting a conductivity enhancing dopant of the second conductivity type through the first source and drain areas of the first conductivity region and the second source and drain areas of the second conductivity region to provide second conductivity type regular LDD implant regions within the substrate operatively adjacent the first transistor gate and to provide second conductivity type halo implant regions within the substrate operatively adjacent the second trans

Abstract: An anode for an electrolytic capacitor includes aluminum foil as a substrate. On the aluminum foil is an alloy including aluminum and a further metal whose oxide has a higher dielectric constant than aluminum oxide. This alloy increases the surface roughness and is in vapor deposited in vacuum in several process steps at different angles of incident. A porous layer thereby is formed and a subsequent anodic oxidation is carried out.

Abstract: In an inverted stagger type thin-film transistor, the preparing process thereof can be simplified, and the unevenness of the thin film transistor prepared thereby can be reduced. That is, disclosed is a preparing method which comprises selectively doping a semiconductor on a gate insulating film with an impurity to form source, drain, and channel forming regions, and conducting a laser annealing to them, or a preparing method which comprises selectively doping the semiconductor region with an impurity by a laser doping method.

Abstract: A flash memory and a method of forming a flash memory, includes forming a polysilicon wordline on a substrate, the wordline having first and second sidewalls, the first sidewall being tapered, with respect to a surface of the substrate, to have a slope angle and the second sidewall having a slope angle greater than the slope angle of the first sidewall. Thereafter, a polysilicon spacer is formed on the second sidewall such that the spacer includes only one side which abuts the second sidewall of the polysilicon wordline.

Abstract: The vertical bipolar transistor includes an SiGe heterojunction base formed by a stack of layers of silicon and silicon-germanium resting on an initial layer of silicon nitride extending over a side insulation region surrounding the upper part of the intrinsic collector. The stack of layers also extends on the surface of the intrinsic collector which lies inside a window formed in the initial layer of silicon nitride.

Abstract: A method for fabricating a monolithically integrated liquid crystal array display and control circuitry on a silicon-on-sapphire structure comprises the steps of: a) forming an epitaxial silicon layer on a sapphire substrate to create a silicon-on-sapphire structure; b) ion implanting the epitaxial silicon layer; c) annealing the silicon-on sapphire structure; d) oxidizing the epitaxial silicon layer to form a silicon dioxide layer from portion of the epitaxial silicon layer so that a thinned epitaxial silicon layer remains; e) removing the silicon dioxide layer to expose the thinned epitaxial silicon layer; f) fabricating an array of pixels from the thinned epitaxial silicon layer; and g) fabricating integrated circuitry from the thinned epitaxial silicon layer which is operably coupled to modulate the pixels. The thinned epitaxial silicon supports the fabrication of device quality circuitry which is used to control the operation of the pixels.

Abstract: The semiconductor device comprises a semiconductor substrate 10 of a first conduction-type, first wells 20a, 20b of a second conduction-type formed in a first region on the primary surface of the semiconductor substrate 10, a second well 22a formed in a second region on the primary surface of the semiconductor substrate 10 other than the first region, a third well 22b of the first conduction-type formed in the first well, and high-concentration impurity-doped layers 26 of the first conduction-type formed in deep portions of the semiconductor substrate spaced from the primary surface of the semiconductor device in device regions. In the semiconductor device having triple wells according to the present invention, the high-concentration impurity-doped layers are formed in deep portions inside of the device regions. Accordingly, in the case where the wells have a low concentration so that the transistors have a low threshold voltage, the deep portions of the wells can independently have a high concentration.

Abstract: CMOS transistors, i.e., N- and P-type transistors, are formed with substantially the same gate length and source/drain regions with lightly doped extensions. Embodiments include sequentially: ion implanting an N-type impurity, e.g. As, to form the N- type transistor shallow source/drain implants; forming relatively thin first sidewall spacers on the gates of both transistors; ion implanting a P-type impurity, e.g. BF2, to form shallow source/drain extension implants for the P-type transistor; forming relatively thick side wall spacers on the first sidewall spacers of both transistors; ion implanting, e.g. As, to form moderately or heavily doped N-type implants; activation annealing at a first temperature, e.g., about 1050° C. to form the shallow N- and P-type source/drain extensions and moderately or heavily doped P-type source/drain regions; ion implanting a P-type impurity, e.g.

Abstract: A method and apparatus of making high energy implanted photodiode that is self aligned with the transfer gate, the high energy implant is defined by providing a substrate, or well, of a first conductivity type, defining a charge coupled device within the substrate, or well, such that gate electrode layers are allowed to exist over areas to contain photodiodes during construction of the charge coupled device, patterning a masking layer to block high energy implants such that openings in the masking layer are formed over the areas of the photodiodes, anisotropically etching down through the gate electrode over the photodiodes to the gate dielectric material, implanting photodiodes with high-energy ions of a second conductivity type opposite the first conductivity type and creating a pinned photodiode by employing a shallow implant of the first conductivity type. The apparatus made by this method yields a photodiode employing high energy ions to form the P/N junction that is self aligned with the transfer gate.

Abstract: An electrical interconnection method includes: a) providing two conductive layers separated by an insulating material on a semiconductor wafer; b) etching the conductive layers and insulating material to define and outwardly expose a sidewall of each conductive layer; c) depositing an electrically conductive material over the etched conductive layers and their respective sidewalls; and d) anisotropically a etching the conductive material to define an electrically conductive sidewall link electrically interconnecting the two conductive layers. Such is utilizable to make thin film transistors and other circuitry.

Abstract: The invention relates to a method of manufacturing a (horizontal) MOST, as used, for example, in (BI)CMOS ICs. On either side of a gate electrode (2), the surface of a silicon substrate (10, 11) which is positioned above a gate oxide (IA) is provided with a dielectric layer (1B) at the location where a source (3) and drain (4) are to be formed, which dielectric layer includes a thermal oxide layer (1B) to be formed as the starting layer. The source (3) and/or drain (4) is/are provided with LDD regions (3A, 4A) and the remaining parts (3B, 4B) of the source (3) and drain (4) are provided by an ion implantation (I1) of doping atoms into the silicon substrate (10, 11). A MOST obtained in this way still suffers from so-called short-channel effects, resulting in a substantial dependence of the threshold voltage upon the length of the gate electrode (2), in particular in the case of very short lengths of the gate electrode (2).

Abstract: A semiconductor memory in which a layout margin at the contact hole between wiring layers of a SRAM does not need and the wiring capacity at bit lines is reduced and the high speed processing is made to be possible is provided. The SRAM is constituted of a pair of driving transistors Qd1 and Qd2, a pair of transferring transistors Qt1 and Qt2, high resistance loads R1 and R2, a pair of bit lines BL1 and BL2, and a VCC line and a GND line. Gate electrodes of each transistor and word lines are formed at a first layer, the high resistance loads are formed at a second layer, the VCC line and the GND line are formed at a third layer, and the bit lines are formed at a fourth layer. A shared contact hole using for connecting the high resistance loads to the source/drain area of transistors does not penetrate the other conductive layers. Therefore, the layout margin between the shared contact hole and the other conductive layers becomes unnecessary and the reduction of the cell size becomes possible.

Abstract: A static random-access memory integrated circuit formed on a single substrate includes a storage IGFET formed on the substrate and having a first area and a first capacitance. A gating FET formed on the substrate has an area substantially equal to the first area with a capacitance substantially less than the first capacitance. In one aspect, the storage FET has a substantially thicker gate oxide than the gating FET. In another aspect, the gate oxide of one of the FETs is formed from a different material than that of the other FET. A method for fabricating such IGFETs on a single substrate is also provided in which source and drain regions are formed adjacent the surface of the substrate. A first layer of gate oxide is formed on the surface of the substrate over the channels of the first and the second FETs. The first layer of gate oxide is then covered by a nitride layer which is thereafter etched away over the channel of one of the FETs.

Abstract: A method for forming a transistor comprises the steps of: forming a gate stack on the surface of a semiconductor substrate; implanting a first dose of an impurity into the substrate at a sufficient energy to penetrate at least a portion of the gate stack to provide a portion of the impurity on the first and second sides of the gate stack, and a portion of the impurity under the gate stack; and forming source/drain regions on the first and second sides of the gate stack. The implant may be at an angle normal to the surface of the substrate at an energy sufficient such that the impurity penetrates the gate stack to reach the channel region. Alternatively, a pair of angled implants at an angle relative to a line normal to the surface of the substrate may be used.

Abstract: A method for forming a tantalum-based anti-reflective coating (ARC) layer begins by forming an MOS metallic gate electrode layer (20) over a substrate (20). The MOS metallic gate electrode layer (20) is covered with an ARC layer (22). The ARC layer is preferably tantalum pentoxide or a tantalum pentoxide layer doped with one or more of nitrogen atoms and/or silicon atoms. The layers (22 and 20) are then selectively masked photoresist (24) that is selectively exposed to deep ultraviolet (DUV) radiation (28). The ARC layer (22) improves lithographic critical dimension (CD) control of the MOS metallic gate during exposure. The final MOS metallic gate is then patterned and etched using a fluorine-chlorine-fluorine time-progressed reactive ion etch (RIE) process, whereby metallic-gate MOS transistors are eventually formed.

Abstract: The present invention discloses a ferroelectric memory device and a method for fabricating the same.

Abstract: A method for creating a self-aligned channel implant with elevated source/drain areas. Forming a thin dielectric layer on top of a silicon substrate, a thick layer of oxide is deposited over this dielectric. An opening is exposed and etched through the layer of oxide, through the dielectric and into the underlying silicon substrate creating a shallow trench in the substrate. By performing the channel implant LDD implant, pocket implant, forming the gate spacers and electrode, removing the thick layer of oxide and forming the S/D regions a gate electrode has been created with elevated S/D regions. By forming the gate spacers, performing channel implant, forming the gate electrode, removing the thick layer of oxide and performing S/D implant a gate electrode has been created with elevated S/D regions and disposable spacers.

Abstract: A method for a T-gate and salicide process that allows narrow bottom gate widths below 0.25 &mgr;m and wide top gate widths to allow silicide gate contacts on the top of the T-gate. A dummy gate composed of an insulating material is formed over the substrate. Then we form LDD regions adjacent to the dummy gate preferably by ion implanting f (I/I) impurity ions into the substrate using the dummy gate as a mask. A pad oxide layer and dielectric layer are formed over the substrate surface. The dielectric layer over the dummy gate is removed preferably by a CMP process. We then remove the dummy gate to form a gate opening exposing the substrate surface. A gate dielectric layer is formed over the substrate surface in the gate opening. We form a polysilicon layer over the dielectric layer and the substrate surface in the gate opening. The polysilicon layer is patterned to form a T-gate. The dielectric layer is removed. We forming source/drain (S/D) regions adjacent to the T-gate by an Ion implant process.

Abstract: A new method of fabricating a sub-quarter micron MOSFET device is achieved. A semiconductor substrate is provided. Isolation regions are formed in this substrate. An oxide layer is provided overlying both the substrate and the isolation regions. The oxide layer is patterned and etched exposing two regions of the substrate. A selective epitaxial growth (SEG) is performed with in situ doping covering the two exposed substrate regions formed during the previous step. The doped SEG regions will form the source and drain contact regions of the MOSFET. The oxide layer region between the two doped SEG regions is then patterned and etched away exposing the substrate. This is followed by a gate oxide formation and either a polysilicon or metal gate deposition. Planarization is then performed on the surface to facilitate interconnection later in the process and to form the final gate structure.

Abstract: A new process is provided to create openings and interconnect patterns for the dual damascene structure. Four layers of dielectric are sequentially deposited over a pattern of interconnect metal. The via hole pattern is defined, the interconnect line pattern is next defined. The via pattern is etched though the upper layer of dielectric and through the stop layer. Only one etch processing step is used to create the desired vias and the desired interconnect line pattern. After the interconnect patterns and vias have been created in the four layers of dielectric, a barrier layer is blanket deposited, the metal is deposited for the dual damascene structure and the interconnect line pattern and polished.