Abstract: A method for forming a sub-quarter micron MOSFET having an elevated source/drain structure is described. A gate electrode is formed over a gate dielectric on a semiconductor substrate. Ions are implanted into the semiconductor substrate to form lightly doped regions using the gate electrode as a mask. Thereafter, dielectric spacers are formed on sidewalls of the gate electrode. A polysilicon layer is deposited overlying the semiconductor substrate, gate electrode, and dielectric spacers wherein the polysilicon layer is heavily doped. The polysilicon layer is etched back to leave polysilicon spacers on the dielectric spacers. Dopant is diffused from the polysilicon spacers into the semiconductor substrate to form source and drain regions underlying the polysilicon spacers.

Abstract: In a semiconductor device including a plurality of memory cells, a deposition preventing film is formed on an interlayer insulating film in which a plurality of holes are formed, or a seed film is selectively formed on the interlayer insulating film and on an inner surface and a bottom surface of the holes. A film of Ru, Ir or Pt is deposited by chemical vapor deposition on the deposition preventing film, or on the interlayer insulating film by utilizing the seed film, under the condition where underlayer dependency occurs. In consequence, lower electrodes are formed in accordance with a pattern of the deposition preventing film or the seed film. A dielectric film is formed on the lower electrodes and the deposition preventing film at a predetermined temperature. The material of the lower electrodes does not lose conduction even when exposed to the predetermined temperature employed for forming the dielectric film. Upper electrodes are further formed on the dielectric film.

Abstract: A method for forming FET devices with attenuated gate induced drain leakage current. There is provided a silicon semiconductor substrate employed within a microelectronics fabrication. There is formed within the silicon substrate field oxide (FOX) dielectric isolation regions defining an active silicon substrate device area. There is formed over the substrate a silicon oxide gate oxide insulation layer employing thermal oxidation. There is then formed over the silicon oxide gate oxide insulation layer a patterned polycrystalline silicon gate electrode layer. There is then thermally oxidized the substrate and polycrystalline silicon gate electrode to form a thicker silicon oxide layer at the edge of the gate electrode and in the adjacent silicon substrate area. There is then etched back the thicker silicon oxide layer from the silicon substrate area adjacent to the gate electrode.

Abstract: Cobalt is sputtered on a silicon wafer in a deposition chamber of a magnetron sputtering system, and is conveyed to a load-lock chamber where a partial pressure of oxygen and/or the water concentration is controlled with introduction of nitrogen so as to present dicobalt disilicide layers from oxidation, thereby improving the production yield and reliability of the silicide layer morphology.

Abstract: A method of fabricating MIS transistors starts with formation of gate electrode portions. Then, high-speed ions are irradiated through an insulating film to implant impurity ions into a semiconductor region by a self-aligning process, followed by total removal of the insulating film. The laminate is irradiated with laser light or other similar intense light to activate the doped semiconductor region. Another method of fabricating MIS transistors begins with formation of a gate-insulating film and gate electrode portions. Then, the gate-insulating film is removed, using the gate electrode portions as a mask. The semiconductor surface is exposed, or a thin insulating film is formed on this surface. High-speed ions are irradiated to perform a self-aligning ion implantation process. A further method of fabricating MIS transistors starts with formation of a gate-insulating film and gate electrode portions.

Abstract: In a method for forming a self-aligned contact in a MOS-type semiconductor device, a gate electrode film is deposited on a semiconductor substrate and an insulating film is deposited on the gate electrode film. The gate electrode film and the insulating film are then patterned such that the portion of the device where the two films are located is higher than any other regions of the device. A side wall insulating film is formed on the side wall of the gate electrode and the insulating film. Source and drain regions are formed in the face of the substrate using the patterned gate electrode film as a mask. A conductor film is then deposited on the exposed surface of the semiconductor substrate, the first insulating film and the side wall insulating film. A flattening film is then deposited to flatten the surface of the semiconductor, and a region of the flattened film and the conductor film which is above the gate electrode film is etched, using a photoresist film as a mask.

Abstract: A method of improving planarity of a photoresist. Before coating the photoresist over a silicon oxide layer, modifying a surface of the silicon oxide layer to enhance an adhesion between the silicon oxide layer and the photoresist. The photoresist flows into trenches of the silicon oxide layer, then the photoresist has good planarity, even after performing a baking process.

Abstract: A process for reducing the dark current generation of an image sensor cell, fabricated on a semiconductor substrate, has been developed. The process features the use of polysilicon pad structure, formed simultaneously with a polysilicon gate structure of a reset transistor, with the polysilicon pad structure located overlying, and contacting, a portion of the top surface of the photodiode element, of the image sensor cell. A small diameter opening, in a composite polysilicon-silicon oxide layer, exposes the portion of photodiode element to be contacted by the polysilicon pad structure. The small diameter opening is created using a procedure which allows the surface of the photodiode element, exposed in the small diameter opening to experience only a minimum of RIE processing at end point, thus minimizing damage to the surface of the photodiode element, and thus reducing dark current generation.

Abstract: A method for manufacturing a semiconductor device including a metal contact and a capacitor. Gate structures are formed on a semiconductor substrate, and a first dielectric layer is formed on the semiconductor substrate to cover the gate structures. A bit line is formed on the first dielectric layer and a second dielectric layer is formed on the first dielectric layer to cover the bit line. A buried contact is formed to be electrically connected to the semiconductor substrate between the gate structures by etching the second dielectric and first dielectric layer. A third dielectric layer is formed on the second dielectric layer. A lower electrode of a capacitor, a dielectric layer, and an upper electrode are formed to be connected to the buried contact. A fourth dielectric layer is formed to cover the capacitor.

Abstract: A method of forming a notched gate structure having substantially vertical sidewalls and a sub-0.05 &mgr;m electrical critical dimension is provided. The method includes forming a conductive layer on an insulating layer; forming a mask on the conductive layer so as to at least protect a portion of the conductive layer; anisotropically etching the conductive layer not protected by the mask so as to thin the conductive layer to a predetermined thickness and to form a conductive feature underlying the mask, the conductive feature having substantially vertical sidewalls; forming a passivating layer at least on the substantially vertical sidewalls; and isotropically etching remaining conductive layer not protected by the mask to remove the predetermined thickness thereby exposing a lower portion of said conductive feature not containing the passivating layer, while simultaneously removing notched regions in the lower portion of the conductive feature.

Abstract: A memory cell of a non-volatile memory includes a control gate oxide layer having graded portions with greatly reduced stress on a polysilicon floating gate layer. The method of making the control gate oxide layer preferably includes growing a first oxide portion by upwardly ramping the polysilicon floating gate layer to a first temperature lower than a glass transition temperature, and exposing the polysilicon floating gate layer to an oxidizing ambient at the first temperature and for a first time period. Also, the method includes growing a second oxide portion between the first oxide portion and the polysilicon floating gate layer by exposing the polysilicon floating gate layer to an oxidizing ambient at a second temperature higher than the glass transition temperature for a second time period. The second oxide portion may have a thickness in a range of about 25 to 75% of a total thickness of the graded, grown, control gate oxide layer.

Abstract: A ferroelectric memory device, e.g., nonvolatile, has an effective layout by eliminating a separate cell plate line. The ferroelectric memory device includes first and second split word lines formed over first and second active regions of a semiconductor substrate, and the first and second active regions are isolated from each other. Source and drain regions are formed in the first active region on both sides of the first split word line and the second active region on both sides of the second split word line. A conductive barrier layer, a first capacitor electrode and a ferroelectric layer are sequentially formed on the first and second split word lines. Two second capacitor electrodes with one connected to one of the source and drain regions of the second active region is formed over the first split word line. The other one is connected to one of the source and drain regions of the first active region and is formed over the second split word line.

Abstract: In a thin film semiconductor device having a substrate (1), an active layer (3, 6, 9), a gate insulation layer (4), and a gate electrode (5), said active layer is produced through the steps of producing an amorphous silicon layer on said substrate through a CVD process by using a gas made up of poly silane SinH2(n+1), where n is an integer, and chloride gas, and effecting solid phase growth to produce said amorphous silicon layer. The addition of chlorine to the CVD gas used in producing the amorphous silicon layer makes it possible to produce the amorphous silicon layer at a lower temperature with a rapid growth rate. A thin film semiconductor device thus produced has the advantages of high mobility and low threshold voltage.

Abstract: A semiconductor device in which the number of steps intrinsic to a memory cell is reduced to as small a value as possible to realize reduction in cell size and invulnerability against software error. A gate oxide film 306 and a capacitance insulating film 310 are formed by one and the same oxide film forming step, while a gate electrode 305 and a charge holding electrode 309 are formed by one and the same electrode forming step. A capacitance electrode connecting local interconnection 311 and a bit line connection local connection 312 are formed by the same interconnection forming step whilst active areas 303 neighboring in the word line direction are arranged with an offset of one gate electrode 305. An area of the isolation film 302 between extending word lines is arrayed adjacent to the Z-Z′ direction of the capacitance forming diffusion layer 307 of the active area 303.

Abstract: A method of forming a notched gate structure having substantially vertical sidewalls and a sub-0.05 &mgr;m electrical critical dimension is provided. The method includes forming a conductive layer on an insulating layer; forming a mask on the conductive layer so as to at least protect a portion of the conductive layer; anisotropically etching the conductive layer not protected by the mask so as to thin the conductive layer to a predetermined thickness and to form a conductive feature underlying the mask, the conductive feature having substantially vertical sidewalls; forming a passivating layer at least on the substantially vertical sidewalls; and isotropically etching remaining conductive layer not protected by the mask to remove the predetermined thickness thereby exposing a lower portion of said conductive feature not containing the passivating layer, while simultaneously removing notched regions in the lower portion of the conductive feature.

Abstract: Methods are provided that use disposable and permanent films to dope underlying layers through diffusion. Additionally, methods are provided that use disposable films during implantation doping and that provide a surface from which to dope underlying materials. Some of these disposable films can be created from a traditionally non-disposable film and made disposable. In this manner, solvents may be used that do not etch underlying layers of silicon-based materials. Preferably, deep implantation is performed to form source/drain regions, then an anneal step is performed to activate the dopants. A conformal layer is deposited and implanted with dopants. One or more anneal steps are performed to create very shallow extensions in the source/drain regions.

Abstract: A novel method and structure are described for making capacitor-under-bit line (CUB) DRAM cells with improved overlay margins between bit lines and capacitor top electrodes. After insulating the FETs with a first insulating layer, a second insulating layer is deposited and first openings are etched for capacitor bottom electrodes. A first conducting layer is deposited. A photoresist layer sufficiently thick is deposited to fill the first openings and form a planar surface. A novel photomask design is used to form second openings between adjacent capacitors in the first openings and partially extending over the first openings. The second openings are recessed to the first conducting layer. The first conducting layer is removed and the underlying second insulating layer is recessed. A thin interelectrode layer is deposited.

Abstract: The invention encompasses a method of forming an opening in a substrate. A first expanse of a first material is formed over the substrate, and such expanse comprises a sidewall edge. A second material is formed along the sidewall edge, and subsequently a second expanse of the first material is formed over the substrate and separated from the first expanse by the second material. The first and second expanses together define a mask. The second material is removed with an etch selective for the second material relative to the first material to form an opening extending through the mask. The substrate is etched through the opening in the mask to extend the opening into the substrate. In a particular embodiment of the invention, the opening is filled with insulative material to form a trenched isolation region. In another embodiment of the invention, the opening is filled with a conductive material to form a transistor gate.

Abstract: A process for forming a high dielectric constant, (High K), layer, for a metal-oxide-metal, capacitor structure, featuring localized oxidation of an underlying metal layer, performed at a temperature higher than the temperature experienced by surrounding structures, has been developed. A first iteration of this process features the use of a laser ablation procedure, performed to a local region of an underlying metal layer, in an oxidizing ambient. The laser ablation procedure creates the desired, high temperature, only at the laser spot, allowing a high K layer to be created at this temperature, while the surrounding structures on a semiconductor substrate, not directly exposed to the laser ablation procedure remain at lower temperatures.

Abstract: A method of forming a memory device (e.g., a DRAM) including array and peripheral circuitry. A plurality of undoped polysilicon gates 58 are formed. These gates 58 are classed into three groups; namely, first conductivity type peripheral gates 58p, second conductivity type peripheral gates 58n, and array gates 58a. The array gates 58a and the first conductivity type peripheral gates 58n are masked such that the second conductivity type peripheral gates 58p remain unmasked. A plurality of second conductivity type peripheral transistors can then be formed by doping each of the second conductivity type peripheral gates 58p, while simultaneously doping a first and a second source/drain region 84 adjacent each of the second conductivity type peripheral gates 58p. The second conductivity type peripheral gates 58p are then masked such that the first conductivity type peripheral gates 58n remain unmasked.