Abstract: A high voltage transistor exhibiting high gated diode breakdown voltage is formed while avoiding an excessive number of costly masking steps. Embodiments include providing a high gated diode breakdown voltage by masking the high voltage junctions from the conventional field implant, masking the source/drain regions from the conventional threshold adjust implant, providing a thick gate oxide layer, employing a very lightly doped n-type implant in lieu of conventional n+ and LDD implants, and forming contacts to the source and drain regions at a minimum distance from the gate.

Abstract: In a memory device of an SRAM, a threshold voltage (Vthn) of each driving MOS transistor consisting of the N-type MOS transistor is set larger than a threshold voltage (Vthp) of each MOS transistor for selecting an address consisting of the P-type MOS transistor.

Abstract: A method for fabricating split-gate flash memory cells is disclosed. In this method, the field oxide is formed after the formation of the poly-1 stripes, which eventually become the floating gates, by oxide growth, thus, the misalignment problems often encountered in the prior art processes between the floating gates and the field oxide layers are eliminated or at least minimized. The method also includes the step of forming a dummy CVD dielectric sidewall spacer with a predetermined thickness before the formation of the poly-2 layer, which eventually become the control gates; this greatly eliminates or at least minimizes the disparity in the peripheral control gate lengths between mirror (adjacent) cells. Both of these improvements can significantly contribute to the reduction of cell size without involving expensive upgrades in processing equipment.

Abstract: The invention provides a semiconductor device, having a variety of functions such as a bistable memory and a logic circuit, in which a MOS semiconductor element, a resonance tunnel diode, a hot electron transistor and the like are formed on a common substrate. An n-type Si layer and a p-type Si layer surrounded with an isolation oxide film are formed on an SOI substrate. A mask oxide film and a gate oxide film are formed, and the n-type Si layer is subjected to crystal anisotropic etching by using the mask oxide film as a mask, so as to change the n-type Si layer into the shape of a thin Si plate. After first and second tunnel oxide films are formed on side faces of this n-type Si layer, first and second polysilicon electrodes of a resonance tunnel diode and a polysilicon electrode working as a gate electrode of a MOS semiconductor element are formed out of a common polysilicon film. Thus, a Si/SiO2 type quantum device can be manufactured with ease at a low cost.

Abstract: A method of fabricating a static random access memory. A substrate having a gate is provided. A source/drain region is formed in the substrate beside the gate. A metal silicide layer is formed on the source/drain region and the gate region. A conductive line which is electrically coupled to the metal silicide layer on the source/drain region is formed over the substrate. A dielectric layer having a via is formed over the substrate. A portion of the conductive line is exposed by the via. A polysilicon conductive line is formed conformably to the via and the dielectric layer. The polysilicon conductive line is electrically coupled to the conductive line. An ion implantation is performed to form a poly load of the static random access memory.

Abstract: A method is provided for fabricating a transistor, the method including forming a dielectric layer above a structure, forming a first polysilicon layer above the dielectric layer and forming a sacrificial region above the first polysilicon layer. The method also includes forming a second polysilicon layer above the first polysilicon layer and adjacent the sacrificial region. The method further includes removing the sacrificial region to form an opening in the second polysilicon layer, the opening having sidewalls, and forming dielectric spacers on the sidewalls of the opening. In addition, the method includes forming a gate dielectric within the opening above the first polysilicon layer and forming a gate conductor above the gate dielectric.

Abstract: A method for forming a semiconductor device to produce graded doping in the source region and the drain region includes the steps of implanting the gate material, usually a polysilicon, with a dopant ion that varies the level of oxide formation on the gate. The dopant ion is driven into undoped polysilicon. Nitrogen ions, may also be implanted in the polysilicon to contain the previously implanted ions. For N-type transistors, typically arsenic is implanted. For P-type transistors, typically boron is implanted. Gates are formed. The gate structure is then oxidized. The oxidation process is controlled to grow a desired thickness of silicon dioxide on the gate. The portion of the gate carrying the dopant grows silicon dioxide either more quickly or more slowly. An isotropic etch can then used to remove a portion of the silicon oxide and form a knob on each sidewall of the gate.

Abstract: A vertical FET is fabricated by etching through a contact layer into a drift layer on a compound semiconductor substrate to form a plurality of mesas, each mesa having an upper surface and each adjacent pair of mesas defining therebetween a trench with sidewalls and a bottom. A conductive layer is conformally deposited over the plurality of mesas and the trenches and anisotropically etched to form contacts on the sidewalls of the trenches and depositing source contacts on the upper surfaces of the mesas and a drain contact on a reverse side of the substrate.

Abstract: A semiconductor component comprises a substrate (101), a two flexible pressure sensor diaphragms (106, 303) supported by the substrate (101), and a fixed electrode (203) between the two diaphragms (106, 303). The two diaphragms (106, 303) and the fixed electrode (203) are electrodes of two differential capacitors. The substrate (101) has a hole (601) extending from one surface (107) of the substrate (101) to an opposite surface (108) of the substrate (101). The hole (601) is located underneath the two diaphragms (106, 303), and the hole (601) at the opposite surfaces (107, 108) of the substrate (101) is preferably larger than the hole (601) at an interior portion of the substrate (101).

Abstract: A method is provided for manufacturing a capacitor having a generally crosssectionally modified T-shaped structure with a rough surface to serve as a lower capacitor plate, and having another dielectric layer and another conducting layer to construct an upper capacitor plate. Such a structure not only significantly increases the surface area of the capacitor but is conducive to the subsequent planarization process.

Abstract: A method for increasing the operating voltage of a transistor formed on a substrate of a first conductivity region of a second conductivity type in a surface of the substrate. An N-well adjust region of the first conductivity type is then formed in the N-well region. The N-well adjust region extends to a first depth in the N-well region. A double diffusion well of the first conductivity type is then formed in the N-well. The double diffusion well extends to a second depth greater than the first depth of the N-well adjust region, and contains a portion of the N-well. Two N- channel stop regions are then formed in the N-well. The two N-channel stop regions extending to a third depth greater than the depth of the N-well adjust region, and contain a portion of the N-well.

Abstract: In a DRAM, a plurality of first MOSFETs are formed in a cell region on a semiconductor substrate based on the minimum design rule, and a first gate side-wall having a side-wall insulation film is formed on the side-wall portion of a first gate electrode of each of the first MOSFETs. At least one second MOSFET is formed in a peripheral circuit region on the semiconductor substrate, and a second gate side-wall having side-wall insulation films is formed on the side-wall portion of a second gate electrode of the second MOSFET. Both the first MOSFETs, which is capable of forming a fine contact hole self-aligned with the first gate electrode, and the second MOSFET, which is capable of sufficiently mitigating the parasitic resistance while suppressing the short channel effect, can be formed on the same substrate.

Abstract: A MOS field effect transistor device and fabrication method thereof are provided, which include a non-uniformly doped well region composed of (1) a first portion thereof which is contiguous to a source or drain region, and situated under a gate electrode, and has a first concentration of said first conductive type impurities, and (2) a second.sub.-- portion which has a second concentration higher than the first concentration of said first conductive type impurities. This structure of the field effect transistor has advantages such as, for example, suppressing short channel effects, increasing source or drain junction breakdown voltages and improving high frequency characteristics of the transistor.

Abstract: In one aspect of the invention, a semiconductor processing method includes: a) providing a semiconductor substrate; b) defining a first conductivity type region and a second conductivity type region of the semiconductor substrate; c) providing a first transistor gate over the first type region which defines a first source area and a first drain area operatively adjacent thereto; d) providing a second transistor gate over the second type region which defines a second source area and a second drain area operatively adjacent thereto; and e) blanket implanting a conductivity enhancing dopant of the second conductivity type through the first source and drain areas of the first conductivity region and the second source and drain areas of the second conductivity region to provide second conductivity type regular LDD implant regions within the substrate operatively adjacent the first transistor gate and to provide second conductivity type halo implant regions within the substrate operatively adjacent the second trans

Abstract: A MOS transistor having a multilevel gate oxide layer is provided for use in an ESD protection circuit. A thick gate oxide layer near the drain insures that the transistor has a relatively large drain to gate breakdown voltage. A thin gate oxide layer near the source permits the gate voltage to turn the transistor on and off with rapid switching speeds. The thick portion of the MOS transistor multilevel gate oxide layer is formed with a local oxidation of silicon (LOCOS) process, while the thin gate layer is formed in a separate step. An ESD protection circuit and method for fabricating the above-mentioned multilevel gate oxide layer MOS transistor are also provided.

Abstract: In thin film transistors (TFTs) having an active layer of crystalline silicon adapted for mass production, a catalytic element is introduced into doped regions of an amorphous silicon film by ion implantation or other means. This film is crystallized at a temperature below the strain point of the glass substrate. Further, a gate insulating film and a gate electrode are formed. Impurities are introduced by a self-aligning process. Then, the laminate is annealed below the strain point of the substrate to activate the dopant impurities. On the other hand, Nickel or other element is also used as a catalytic element for promoting crystallization of an amorphous silicon film. First, this catalytic element is applied in contact with the surface of the amorphous silicon film. The film is heated at 450 to 650.degree. C. to create crystal nuclei. The film is further heated at a higher temperature to grow the crystal grains. In this way, a crystalline silicon film having improved crystallinity is formed.

Abstract: A method and structure are provided for an IGFET which has elevated source/drain regions and polished gate electrode. The IGFET provides raised doped polysilicon regions between the source/drain areas and subsequent metallization layers. The doped polysilicon regions are scalable. Integration of elevated source/drain regions provides a shallow junction for high performance IGFET design. A refractory metal gate is provided without sacrificing the fabrication advantage of self-aligned techniques. A method to produce an IGFET which incorporates both of the above advantages into a single device, with relatively few process steps, is also provided. Fabricating the gate electrode in this manner will enable metal gate electrodes to be integrated with source/drain structure.

Abstract: The present invention includes forming nitrogen-doped amorphous silicon layer on the gate structure and on a pad oxide. Nitride spacers are formed on the side walls of the gate structure. Then, the nitride spacers and the cap nitride are both removed by wet etching. Next, an ion implantation is carried out to dope dopants into the gate and in the N well. Doped regions for the NMOS device are next formed in the P well by performing a further ion implantation. An oxidation is performed to convert the nitrogen-doped amorphous silicon layer to a nitrogen-doped oxide layer. An ultra-shallow source and drain junctions and the extended source and drain are obtained by using the amorphous silicon layer as a diffusion source. Next, nitrogen spacers on the side walls of the oxide are formed. The oxide on the top of the gate and uncovered by the spacers are removed during the etching to form spacers. Self-aligned silicide (SALICIDE) and polycide are respectively formed on the exposed substrate and gate.

Abstract: A method for producing a via hole to a doped region in a semiconductor device, including the steps of: producing the doped region in a substrate such that the doped region is limited by insulating regions at least at a surface of the substrate; depositing an undoped silicon layer surface-wide on the substrate; producing a doped region in the silicon layer that overlaps a region for the via hole; selectively removing the undoped silicon of the silicon layer relative to the doped region of the silicon layer; producing an insulating layer surface-wide; and forming the via hole in the insulating layer by selective anisotropic etching relative to the doped region of the silicon layer.

Abstract: A DMOS device in a complex integrated circuit having a well region defined by a buried isolation region and an overlapping deep drain region within an epitaxial layer formed over a substrate, a body region having two source regions within the well region, insulated gates over the two source regions, and a Schottky contact over a central portion of the well region and spaced from the body region. The Schottky contact defines a Schottky diode within the epitaxial layer for diverting current from the substrate in the event of a below ground effect or an oversupply effect. The invention reduces or eliminates altogether the effects of parasitic transistors in the complex integrated circuit.